1.\" 2.\" Copyright (c) 2003 Bruce M Simpson <bms@spc.org> 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24.\" SUCH DAMAGE. 25.\" 26.\" $FreeBSD$ 27.\" 28.Dd May 21, 2003 29.Dt PCI 9 30.Os 31.Sh NAME 32.Nm pci , 33.Nm pci_read_config , 34.Nm pci_write_config , 35.Nm pci_enable_busmaster , 36.Nm pci_disable_busmaster , 37.Nm pci_enable_io , 38.Nm pci_disable_io , 39.Nm pci_set_powerstate , 40.Nm pci_get_powerstate , 41.Nm pci_find_bsf , 42.Nm pci_find_device 43.Nd PCI bus interface 44.Sh SYNOPSIS 45.In sys/bus.h 46.In dev/pci/pcivar.h 47.In dev/pci/pcireg.h 48.In machine/pci_cfgreg.h 49.Ft void 50.Fn pci_write_config "device_t dev" "int reg" "uint32_t val" "int width" 51.Ft int 52.Fn pci_enable_busmaster "device_t dev" 53.Ft int 54.Fn pci_disable_busmaster "device_t dev" 55.Ft int 56.Fn pci_enable_io "device_t dev" "int space" 57.Ft int 58.Fn pci_disable_io "device_t dev" "int space" 59.Ft int 60.Fn pci_set_powerstate "device_t dev" "int state" 61.Ft int 62.Fn pci_get_powerstate "device_t dev" 63.Ft uint32_t 64.Fn pci_read_config "device_t dev" "int reg" "int width" 65.Ft device_t 66.Fn pci_find_bsf "uint8_t bus" "uint8_t slot" "uint8_t func" 67.Ft device_t 68.Fn pci_find_device "uint16_t vendor" "uint16_t device" 69.Sh DESCRIPTION 70The 71.Nm 72set of functions are used for managing PCI devices. 73.Pp 74The 75.Fn pci_read_config 76function is used to read data from the PCI configuration 77space of the device 78.Fa dev , 79at offset 80.Fa reg , 81with 82.Fa width 83specifying the size of the access. 84.Pp 85The 86.Fn pci_write_config 87function is used to write the value 88.Fa val 89to the PCI configuration 90space of the device 91.Fa dev , 92at offset 93.Fa reg , 94with 95.Fa width 96specifying the size of the access. 97.Pp 98The 99.Fn pci_enable_busmaster 100function enables PCI bus mastering for the device 101.Fa dev , 102by setting the 103.Dv PCIM_CMD_BUSMASTEREN 104bit in the 105.Dv PCIR_COMMAND 106register. 107The 108.Fn pci_disable_busmaster 109function clears this bit. 110.Pp 111The 112.Fn pci_enable_io 113function enables memory or I/O port address decoding for the device 114.Fa dev , 115by setting the 116.Dv PCIM_CMD_MEMEN 117or 118.Dv PCIM_CMD_PORTEN 119bit in the 120.Dv PCIR_COMMAND 121register appropriately. 122The 123.Fn pci_disable_io 124function clears the appropriate bit. 125The 126.Fa space 127argument specifies which resource is affected; this can be either 128.Dv SYS_RES_MEMORY 129or 130.Dv SYS_RES_IOPORT 131as appropriate. 132.Pp 133.Em NOTE : 134These functions should be used in preference to manually manipulating 135the configuration space. 136.Pp 137The 138.Fn pci_get_powerstate 139function returns the current ACPI power state of the device 140.Fa dev . 141If the device does not support power management capabilities, then the default 142state of 143.Dv PCI_POWERSTATE_D0 144is returned. 145The following power states are defined by ACPI: 146.Bl -hang -width ".Dv PCI_POWERSTATE_UNKNOWN" 147.It Dv PCI_POWERSTATE_D0 148State in which device is on and running. 149It is receiving full power from the system and delivering 150full functionality to the user. 151.It Dv PCI_POWERSTATE_D1 152Class-specific low-power state in which device context may or 153may not be lot. 154Busses in this state cannot do anything to the bus, to 155force devices to lose context. 156.It Dv PCI_POWERSTATE_D2 157Class-specific low-power state in which device context may or 158may not be lost. 159Attains greater power savings than 160.Dv PCI_POWERSTATE_D1 . 161Busses in this state can cause devices to lose some context. 162Devices 163.Em must 164be prepared for the bus to be in this state or higher. 165.It Dv PCI_POWERSTATE_D3 166State in which the device is off and not running. 167Device context is lost, and power from the device can 168be removed. 169.It Dv PCI_POWERSTATE_UNKNOWN 170State of the device is unknown. 171.El 172.Pp 173The 174.Fn pci_set_powerstate 175function is used to transition the device 176.Fa dev 177to the ACPI power state 178.Fa state . 179It checks to see if the device is PCI 2.2 compliant. 180If so, it checks the 181capabilities pointer to determine which power states the device supports. 182If the device does not have power management capabilities, the default state 183of 184.Dv PCI_POWERSTATE_D0 185is set. 186.Pp 187The 188.Fn pci_find_bsf 189function looks up the 190.Vt device_t 191of a PCI device, given its 192.Fa bus , 193.Fa slot , 194and 195.Fa func . 196.Pp 197The 198.Fn pci_find_device 199function looks up the 200.Vt device_t 201of a PCI device, given its 202.Fa vendor 203and 204.Fa device 205IDs. 206Note that there can be multiple matches for this search; this function 207only returns the first matching device. 208.Sh IMPLEMENTATION NOTES 209The 210.Vt pci_addr_t 211type varies according to the size of the PCI bus address 212space on the target architecture. 213.Sh SEE ALSO 214.Xr pci 4 , 215.Xr pciconf 8 , 216.Xr bus_alloc_resource 9 , 217.Xr bus_dma 9 , 218.Xr bus_release_resource 9 , 219.Xr bus_setup_intr 9 , 220.Xr bus_teardown_intr 9 , 221.Xr devclass 9 , 222.Xr device 9 , 223.Xr driver 9 , 224.Xr rman 9 225.Rs 226.%B FreeBSD Developers' Handbook 227.%T NewBus 228.%O http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/developers-handbook/ 229.Re 230.Rs 231.%A Shanley 232.%A Anderson 233.%B PCI System Architecture 234.%N 2nd Edition 235.%I Addison-Wesley 236.%O ISBN 0-201-30974-2 237.Re 238.Sh AUTHORS 239This man page was written by 240.An Bruce M Simpson Aq bms@spc.org . 241.Sh BUGS 242This manual page does not yet document PAE and how it affects memory-space 243mapping of PCI devices. 244