xref: /freebsd/share/man/man9/pci.9 (revision 1f4bcc459a76b7aa664f3fd557684cd0ba6da352)
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26.\" $FreeBSD$
27.\"
28.Dd December 23, 2015
29.Dt PCI 9
30.Os
31.Sh NAME
32.Nm pci ,
33.Nm pci_alloc_msi ,
34.Nm pci_alloc_msix ,
35.Nm pci_disable_busmaster ,
36.Nm pci_disable_io ,
37.Nm pci_enable_busmaster ,
38.Nm pci_enable_io ,
39.Nm pci_find_bsf ,
40.Nm pci_find_cap ,
41.Nm pci_find_dbsf ,
42.Nm pci_find_device ,
43.Nm pci_find_extcap ,
44.Nm pci_find_htcap ,
45.Nm pci_find_pcie_root_port ,
46.Nm pci_get_max_read_req ,
47.Nm pci_get_powerstate ,
48.Nm pci_get_vpd_ident ,
49.Nm pci_get_vpd_readonly ,
50.Nm pci_iov_attach ,
51.Nm pci_iov_detach ,
52.Nm pci_msi_count ,
53.Nm pci_msix_count ,
54.Nm pci_msix_pba_bar ,
55.Nm pci_msix_table_bar ,
56.Nm pci_pending_msix ,
57.Nm pci_read_config ,
58.Nm pci_release_msi ,
59.Nm pci_remap_msix ,
60.Nm pci_restore_state ,
61.Nm pci_save_state ,
62.Nm pci_set_max_read_req ,
63.Nm pci_set_powerstate ,
64.Nm pci_write_config ,
65.Nm pcie_adjust_config ,
66.Nm pcie_read_config ,
67.Nm pcie_write_config
68.Nd PCI bus interface
69.Sh SYNOPSIS
70.In sys/bus.h
71.In dev/pci/pcireg.h
72.In dev/pci/pcivar.h
73.Ft int
74.Fn pci_alloc_msi "device_t dev" "int *count"
75.Ft int
76.Fn pci_alloc_msix "device_t dev" "int *count"
77.Ft int
78.Fn pci_disable_busmaster "device_t dev"
79.Ft int
80.Fn pci_disable_io "device_t dev" "int space"
81.Ft int
82.Fn pci_enable_busmaster "device_t dev"
83.Ft int
84.Fn pci_enable_io "device_t dev" "int space"
85.Ft device_t
86.Fn pci_find_bsf "uint8_t bus" "uint8_t slot" "uint8_t func"
87.Ft int
88.Fn pci_find_cap "device_t dev" "int capability" "int *capreg"
89.Ft device_t
90.Fn pci_find_dbsf "uint32_t domain" "uint8_t bus" "uint8_t slot" "uint8_t func"
91.Ft device_t
92.Fn pci_find_device "uint16_t vendor" "uint16_t device"
93.Ft int
94.Fn pci_find_extcap "device_t dev" "int capability" "int *capreg"
95.Ft int
96.Fn pci_find_htcap "device_t dev" "int capability" "int *capreg"
97.Ft device_t
98.Fn pci_find_pcie_root_port "device_t dev"
99.Ft int
100.Fn pci_get_max_read_req "device_t dev"
101.Ft int
102.Fn pci_get_powerstate "device_t dev"
103.Ft int
104.Fn pci_get_vpd_ident "device_t dev" "const char **identptr"
105.Ft int
106.Fn pci_get_vpd_readonly "device_t dev" "const char *kw" "const char **vptr"
107.Ft int
108.Fn pci_msi_count "device_t dev"
109.Ft int
110.Fn pci_msix_count "device_t dev"
111.Ft int
112.Fn pci_msix_pba_bar "device_t dev"
113.Ft int
114.Fn pci_msix_table_bar "device_t dev"
115.Ft int
116.Fn pci_pending_msix "device_t dev" "u_int index"
117.Ft uint32_t
118.Fn pci_read_config "device_t dev" "int reg" "int width"
119.Ft int
120.Fn pci_release_msi "device_t dev"
121.Ft int
122.Fn pci_remap_msix "device_t dev" "int count" "const u_int *vectors"
123.Ft void
124.Fn pci_restore_state "device_t dev"
125.Ft void
126.Fn pci_save_state "device_t dev"
127.Ft int
128.Fn pci_set_max_read_req "device_t dev" "int size"
129.Ft int
130.Fn pci_set_powerstate "device_t dev" "int state"
131.Ft void
132.Fn pci_write_config "device_t dev" "int reg" "uint32_t val" "int width"
133.Ft uint32_t
134.Fo pcie_adjust_config
135.Fa "device_t dev"
136.Fa "int reg"
137.Fa "uint32_t mask"
138.Fa "uint32_t val"
139.Fa "int width"
140.Fc
141.Ft uint32_t
142.Fn pcie_read_config "device_t dev" "int reg" "int width"
143.Ft void
144.Fn pcie_write_config "device_t dev" "int reg" "uint32_t val" "int width"
145.In dev/pci/pci_iov.h
146.Ft int
147.Fn pci_iov_attach "device_t dev" "nvlist_t *pf_schema" "nvlist_t *vf_schema"
148.Ft int
149.Fn pci_iov_detach "device_t dev"
150.Sh DESCRIPTION
151The
152.Nm
153set of functions are used for managing PCI devices.
154The functions are split into several groups:
155raw configuration access,
156locating devices,
157device information,
158device configuration,
159and
160message signaled interrupts.
161.Ss Raw Configuration Access
162The
163.Fn pci_read_config
164function is used to read data from the PCI configuration
165space of the device
166.Fa dev ,
167at offset
168.Fa reg ,
169with
170.Fa width
171specifying the size of the access.
172.Pp
173The
174.Fn pci_write_config
175function is used to write the value
176.Fa val
177to the PCI configuration
178space of the device
179.Fa dev ,
180at offset
181.Fa reg ,
182with
183.Fa width
184specifying the size of the access.
185.Pp
186The
187.Fn pcie_adjust_config
188function is used to modify the value of a register in the PCI-express
189capability register set of device
190.Fa dev .
191The offset
192.Fa reg
193specifies a relative offset in the register set with
194.Fa width
195specifying the size of the access.
196The new value of the register is computed by modifying bits set in
197.Fa mask
198to the value in
199.Fa val .
200Any bits not specified in
201.Fa mask
202are preserved.
203The previous value of the register is returned.
204.Pp
205The
206.Fn pcie_read_config
207function is used to read the value of a register in the PCI-express
208capability register set of device
209.Fa dev .
210The offset
211.Fa reg
212specifies a relative offset in the register set with
213.Fa width
214specifying the size of the access.
215.Pp
216The
217.Fn pcie_write_config
218function is used to write the value
219.Fa val
220to a register in the PCI-express capability register set of device
221.Fa dev .
222The offset
223.Fa reg
224specifies a relative offset in the register set with
225.Fa width
226specifying the size of the access.
227.Pp
228.Em NOTE :
229Device drivers should only use these functions for functionality that
230is not available via another
231.Fn pci
232function.
233.Ss Locating Devices
234The
235.Fn pci_find_bsf
236function looks up the
237.Vt device_t
238of a PCI device, given its
239.Fa bus ,
240.Fa slot ,
241and
242.Fa func .
243The
244.Fa slot
245number actually refers to the number of the device on the bus,
246which does not necessarily indicate its geographic location
247in terms of a physical slot.
248Note that in case the system has multiple PCI domains,
249the
250.Fn pci_find_bsf
251function only searches the first one.
252Actually, it is equivalent to:
253.Bd -literal -offset indent
254pci_find_dbsf(0, bus, slot, func);
255.Ed
256.Pp
257The
258.Fn pci_find_dbsf
259function looks up the
260.Vt device_t
261of a PCI device, given its
262.Fa domain ,
263.Fa bus ,
264.Fa slot ,
265and
266.Fa func .
267The
268.Fa slot
269number actually refers to the number of the device on the bus,
270which does not necessarily indicate its geographic location
271in terms of a physical slot.
272.Pp
273The
274.Fn pci_find_device
275function looks up the
276.Vt device_t
277of a PCI device, given its
278.Fa vendor
279and
280.Fa device
281IDs.
282Note that there can be multiple matches for this search; this function
283only returns the first matching device.
284.Ss Device Information
285The
286.Fn pci_find_cap
287function is used to locate the first instance of a PCI capability
288register set for the device
289.Fa dev .
290The capability to locate is specified by ID via
291.Fa capability .
292Constant macros of the form
293.Dv PCIY_xxx
294for standard capability IDs are defined in
295.In dev/pci/pcireg.h .
296If the capability is found, then
297.Fa *capreg
298is set to the offset in configuration space of the capability register set,
299and
300.Fn pci_find_cap
301returns zero.
302If the capability is not found or the device does not support capabilities,
303.Fn pci_find_cap
304returns an error.
305.Pp
306The
307.Fn pci_find_extcap
308function is used to locate the first instance of a PCI-express
309extended capability register set for the device
310.Fa dev .
311The extended capability to locate is specified by ID via
312.Fa capability .
313Constant macros of the form
314.Dv PCIZ_xxx
315for standard extended capability IDs are defined in
316.In dev/pci/pcireg.h .
317If the extended capability is found, then
318.Fa *capreg
319is set to the offset in configuration space of the extended capability
320register set, and
321.Fn pci_find_extcap
322returns zero.
323If the extended capability is not found or the device is not a
324PCI-express device,
325.Fn pci_find_extcap
326returns an error.
327.Pp
328The
329.Fn pci_find_htcap
330function is used to locate the first instance of a HyperTransport capability
331register set for the device
332.Fa dev .
333The capability to locate is specified by type via
334.Fa capability .
335Constant macros of the form
336.Dv PCIM_HTCAP_xxx
337for standard HyperTransport capability types are defined in
338.In dev/pci/pcireg.h .
339If the capability is found, then
340.Fa *capreg
341is set to the offset in configuration space of the capability register set,
342and
343.Fn pci_find_htcap
344returns zero.
345If the capability is not found or the device is not a HyperTransport device,
346.Fn pci_find_htcap
347returns an error.
348.Pp
349The
350.Fn pci_find_pcie_root_port
351function walks up the PCI device hierarchy to locate the PCI-express root
352port upstream of
353.Fa dev .
354If a root port is not found,
355.Fn pci_find_pcie_root_port
356returns
357.Dv NULL .
358.Pp
359The
360.Fn pci_get_vpd_ident
361function is used to fetch a device's Vital Product Data
362.Pq VPD
363identifier string.
364If the device
365.Fa dev
366supports VPD and provides an identifier string,
367then
368.Fa *identptr
369is set to point at a read-only, null-terminated copy of the identifier
370string,
371and
372.Fn pci_get_vpd_ident
373returns zero.
374If the device does not support VPD or does not provide an identifier
375string,
376then
377.Fn pci_get_vpd_ident
378returns an error.
379.Pp
380The
381.Fn pci_get_vpd_readonly
382function is used to fetch the value of a single VPD read-only keyword
383for the device
384.Fa dev .
385The keyword to fetch is identified by the two character string
386.Fa kw .
387If the device supports VPD and provides a read-only value for the
388requested keyword,
389then
390.Fa *vptr
391is set to point at a read-only, null-terminated copy of the value,
392and
393.Fn pci_get_vpd_readonly
394returns zero.
395If the device does not support VPD or does not provide the requested
396keyword,
397then
398.Fn pci_get_vpd_readonly
399returns an error.
400.Ss Device Configuration
401The
402.Fn pci_enable_busmaster
403function enables PCI bus mastering for the device
404.Fa dev ,
405by setting the
406.Dv PCIM_CMD_BUSMASTEREN
407bit in the
408.Dv PCIR_COMMAND
409register.
410The
411.Fn pci_disable_busmaster
412function clears this bit.
413.Pp
414The
415.Fn pci_enable_io
416function enables memory or I/O port address decoding for the device
417.Fa dev ,
418by setting the
419.Dv PCIM_CMD_MEMEN
420or
421.Dv PCIM_CMD_PORTEN
422bit in the
423.Dv PCIR_COMMAND
424register appropriately.
425The
426.Fn pci_disable_io
427function clears the appropriate bit.
428The
429.Fa space
430argument specifies which resource is affected; this can be either
431.Dv SYS_RES_MEMORY
432or
433.Dv SYS_RES_IOPORT
434as appropriate.
435Device drivers should generally not use these routines directly.
436The PCI bus will enable decoding automatically when a
437.Dv SYS_RES_MEMORY
438or
439.Dv SYS_RES_IOPORT
440resource is activated via
441.Xr bus_alloc_resource 9
442or
443.Xr bus_activate_resource 9 .
444.Pp
445The
446.Fn pci_get_max_read_req
447function returns the current maximum read request size in bytes for a
448PCI-express device.
449If the
450.Fa dev
451device is not a PCI-express device,
452.Fn pci_get_max_read_req
453returns zero.
454.Pp
455The
456.Fn pci_set_max_read_req
457sets the PCI-express maximum read request size for
458.Fa dev .
459The requested
460.Fa size
461may be adjusted,
462and
463.Fn pci_set_max_read_req
464returns the actual size set in bytes.
465If the
466.Fa dev
467device is not a PCI-express device,
468.Fn pci_set_max_read_req
469returns zero.
470.Pp
471The
472.Fn pci_get_powerstate
473function returns the current power state of the device
474.Fa dev .
475If the device does not support power management capabilities, then the default
476state of
477.Dv PCI_POWERSTATE_D0
478is returned.
479The following power states are defined by PCI:
480.Bl -hang -width ".Dv PCI_POWERSTATE_UNKNOWN"
481.It Dv PCI_POWERSTATE_D0
482State in which device is on and running.
483It is receiving full power from the system and delivering
484full functionality to the user.
485.It Dv PCI_POWERSTATE_D1
486Class-specific low-power state in which device context may or
487may not be lost.
488Busses in this state cannot do anything to the bus, to
489force devices to lose context.
490.It Dv PCI_POWERSTATE_D2
491Class-specific low-power state in which device context may or
492may not be lost.
493Attains greater power savings than
494.Dv PCI_POWERSTATE_D1 .
495Busses in this state can cause devices to lose some context.
496Devices
497.Em must
498be prepared for the bus to be in this state or higher.
499.It Dv PCI_POWERSTATE_D3
500State in which the device is off and not running.
501Device context is lost, and power from the device can
502be removed.
503.It Dv PCI_POWERSTATE_UNKNOWN
504State of the device is unknown.
505.El
506.Pp
507The
508.Fn pci_set_powerstate
509function is used to transition the device
510.Fa dev
511to the PCI power state
512.Fa state .
513If the device does not support power management capabilities or
514it does not support the specific power state
515.Fa state ,
516then the function will fail with
517.Er EOPNOTSUPP .
518.Pp
519The
520.Fn pci_iov_attach
521function is used to advertise that the given device
522.Pq and associated device driver
523supports PCI Single-Root I/O Virtualization
524.Pq SR-IOV .
525A driver that supports SR-IOV must implement the
526.Xr PCI_IOV_INIT 9 ,
527.Xr PCI_IOV_ADD_VF 9
528and
529.Xr PCI_IOV_UNINIT 9
530methods.
531This function should be called during the
532.Xr DEVICE_ATTACH 9
533method.
534If this function returns an error, it is recommended that the device driver
535still successfully attaches, but runs with SR-IOV disabled.
536The
537.Fa pf_schema
538and
539.Fa vf_schema
540parameters are used to define what device-specific configuration parameters the
541device driver accepts when SR-IOV is enabled for the Physical Function
542.Pq PF
543and for individual Virtual Functions
544.Pq VFs
545respectively.
546See
547.Xr pci_iov_schema 9
548for details on how to construct the schema.
549If either the
550.Pa pf_schema
551or
552.Pa vf_schema
553is invalid or specifies parameter names that conflict with parameter names that
554are already in use,
555.Fn pci_iov_attach
556will return an error and SR-IOV will not be available on the PF device.
557If a driver does not accept configuration parameters for either the PF device
558or the VF devices, the driver must pass an empty schema for that device.
559The SR-IOV infrastructure takes ownership of the
560.Fa pf_schema
561and
562.Fa vf_schema
563and is responsible for freeing them.
564The driver must never free the schemas itself.
565.Pp
566The
567.Fn pci_iov_detach
568function is used to advise the SR-IOV infrastructure that the driver for the
569given device is attempting to detach and that all SR-IOV resources for the
570device must be released.
571This function must be called during the
572.Xr DEVICE_DETACH 9
573method if
574.Fn pci_iov_attach
575was successfully called on the device and
576.Fn pci_iov_detach
577has not subsequently been called on the device and returned no error.
578If this function returns an error, the
579.Xr DEVICE_DETACH 9
580method must fail and return an error, as detaching the PF driver while VF
581devices are active would cause system instability.
582This function is safe to call and will always succeed if
583.Fn pci_iov_attach
584previously failed with an error on the given device, or if
585.Fn pci_iov_attach
586was never called on the device.
587.Pp
588The
589.Fn pci_save_state
590and
591.Fn pci_restore_state
592functions can be used by a device driver to save and restore standard PCI
593config registers.
594The
595.Fn pci_save_state
596function must be invoked while the device has valid state before
597.Fn pci_restore_state
598can be used.
599If the device is not in the fully-powered state
600.Pq Dv PCI_POWERSTATE_D0
601when
602.Fn pci_restore_state
603is invoked,
604then the device will be transitioned to
605.Dv PCI_POWERSTATE_D0
606before any config registers are restored.
607.Ss Message Signaled Interrupts
608Message Signaled Interrupts
609.Pq MSI
610and
611Enhanced Message Signaled Interrupts
612.Pq MSI-X
613are PCI capabilities that provide an alternate method for PCI
614devices to signal interrupts.
615The legacy INTx interrupt is available to PCI devices as a
616.Dv SYS_RES_IRQ
617resource with a resource ID of zero.
618MSI and MSI-X interrupts are available to PCI devices as one or more
619.Dv SYS_RES_IRQ
620resources with resource IDs greater than zero.
621A driver must ask the PCI bus to allocate MSI or MSI-X interrupts
622using
623.Fn pci_alloc_msi
624or
625.Fn pci_alloc_msix
626before it can use MSI or MSI-X
627.Dv SYS_RES_IRQ
628resources.
629A driver is not allowed to use the legacy INTx
630.Dv SYS_RES_IRQ
631resource if MSI or MSI-X interrupts have been allocated,
632and attempts to allocate MSI or MSI-X interrupts will fail if the
633driver is currently using the legacy INTx
634.Dv SYS_RES_IRQ
635resource.
636A driver is only allowed to use either MSI or MSI-X,
637but not both.
638.Pp
639The
640.Fn pci_msi_count
641function returns the maximum number of MSI messages supported by the
642device
643.Fa dev .
644If the device does not support MSI,
645then
646.Fn pci_msi_count
647returns zero.
648.Pp
649The
650.Fn pci_alloc_msi
651function attempts to allocate
652.Fa *count
653MSI messages for the device
654.Fa dev .
655The
656.Fn pci_alloc_msi
657function may allocate fewer messages than requested for various
658reasons including requests for more messages than the device
659.Fa dev
660supports,
661or if the system has a shortage of available MSI messages.
662On success,
663.Fa *count
664is set to the number of messages allocated and
665.Fn pci_alloc_msi
666returns zero.
667The
668.Dv SYS_RES_IRQ
669resources for the allocated messages will be available at consecutive
670resource IDs beginning with one.
671If
672.Fn pci_alloc_msi
673is not able to allocate any messages,
674it returns an error.
675Note that MSI only supports message counts that are powers of two;
676requests to allocate a non-power of two count of messages will fail.
677.Pp
678The
679.Fn pci_release_msi
680function is used to release any allocated MSI or MSI-X messages back
681to the system.
682If any MSI or MSI-X
683.Dv SYS_RES_IRQ
684resources are allocated by the driver or have a configured interrupt
685handler,
686this function will fail with
687.Er EBUSY .
688The
689.Fn pci_release_msi
690function returns zero on success and an error on failure.
691.Pp
692The
693.Fn pci_msix_count
694function returns the maximum number of MSI-X messages supported by the
695device
696.Fa dev .
697If the device does not support MSI-X,
698then
699.Fn pci_msix_count
700returns zero.
701.Pp
702The
703.Fn pci_msix_pba_bar
704function returns the offset in configuration space of the Base Address Register
705.Pq BAR
706containing the MSI-X Pending Bit Array (PBA) for device
707.Fa dev .
708The returned value can be used as the resource ID with
709.Xr bus_alloc_resource 9
710and
711.Xr bus_release_resource 9
712to allocate the BAR.
713If the device does not support MSI-X,
714then
715.Fn pci_msix_pba_bar
716returns -1.
717.Pp
718The
719.Fn pci_msix_table_bar
720function returns the offset in configuration space of the BAR
721containing the MSI-X vector table for device
722.Fa dev .
723The returned value can be used as the resource ID with
724.Xr bus_alloc_resource 9
725and
726.Xr bus_release_resource 9
727to allocate the BAR.
728If the device does not support MSI-X,
729then
730.Fn pci_msix_table_bar
731returns -1.
732.Pp
733The
734.Fn pci_alloc_msix
735function attempts to allocate
736.Fa *count
737MSI-X messages for the device
738.Fa dev .
739The
740.Fn pci_alloc_msix
741function may allocate fewer messages than requested for various
742reasons including requests for more messages than the device
743.Fa dev
744supports,
745or if the system has a shortage of available MSI-X messages.
746On success,
747.Fa *count
748is set to the number of messages allocated and
749.Fn pci_alloc_msix
750returns zero.
751For MSI-X messages,
752the resource ID for each
753.Dv SYS_RES_IRQ
754resource identifies the index in the MSI-X table of the
755corresponding message.
756A resource ID of one maps to the first index of the MSI-X table;
757a resource ID two identifies the second index in the table, etc.
758The
759.Fn pci_alloc_msix
760function assigns the
761.Fa *count
762messages allocated to the first
763.Fa *count
764table indicies.
765If
766.Fn pci_alloc_msix
767is not able to allocate any messages,
768it returns an error.
769Unlike MSI,
770MSI-X does not require message counts that are powers of two.
771.Pp
772The BARs containing the MSI-X vector table and PBA must be
773allocated via
774.Xr bus_alloc_resource 9
775before calling
776.Fn pci_alloc_msix
777and must not be released until after calling
778.Fn pci_release_msi .
779Note that the vector table and PBA may be stored in the same BAR or in
780different BARs.
781.Pp
782The
783.Fn pci_pending_msix
784function examines the
785.Fa dev
786device's PBA
787to determine the pending status of the MSI-X message at table index
788.Fa index .
789If the indicated message is pending,
790this function returns a non-zero value;
791otherwise,
792it returns zero.
793Passing an invalid
794.Fa index
795to this function will result in undefined behavior.
796.Pp
797As mentioned in the description of
798.Fn pci_alloc_msix ,
799MSI-X messages are initially assigned to the first N table entries.
800A driver may use a different distribution of available messages to
801table entries via the
802.Fn pci_remap_msix
803function.
804Note that this function must be called after a successful call to
805.Fn pci_alloc_msix
806but before any of the
807.Dv SYS_RES_IRQ
808resources are allocated.
809The
810.Fn pci_remap_msix
811function returns zero on success,
812or an error on failure.
813.Pp
814The
815.Fa vectors
816array should contain
817.Fa count
818message vectors.
819The array maps directly to the MSI-X table in that the first entry in
820the array specifies the message used for the first entry in the MSI-X
821table,
822the second entry in the array corresponds to the second entry in the
823MSI-X table,
824etc.
825The vector value in each array index can either be zero to indicate
826that no message should be assigned to the corresponding MSI-X table entry,
827or it can be a number from one to N
828.Po
829where N is the count returned from the previous call to
830.Fn pci_alloc_msix
831.Pc
832to indicate which of the allocated messages should be assigned to the
833corresponding MSI-X table entry.
834.Pp
835If
836.Fn pci_remap_msix
837succeeds,
838each MSI-X table entry with a non-zero vector will have an associated
839.Dv SYS_RES_IRQ
840resource whose resource ID corresponds to the table index as described
841above for
842.Fn pci_alloc_msix .
843MSI-X table entries that with a vector of zero will not have an
844associated
845.Dv SYS_RES_IRQ
846resource.
847Additionally,
848if any of the original messages allocated by
849.Fn pci_alloc_msix
850are not used in the new distribution of messages in the MSI-X table,
851they will be released automatically.
852Note that if a driver wishes to use fewer messages than were allocated by
853.Fn pci_alloc_msix ,
854the driver must use a single, contiguous range of messages beginning
855with one in the new distribution.
856The
857.Fn pci_remap_msix
858function will fail if this condition is not met.
859.Sh IMPLEMENTATION NOTES
860The
861.Vt pci_addr_t
862type varies according to the size of the PCI bus address
863space on the target architecture.
864.Sh SEE ALSO
865.Xr pci 4 ,
866.Xr pciconf 8 ,
867.Xr bus_alloc_resource 9 ,
868.Xr bus_dma 9 ,
869.Xr bus_release_resource 9 ,
870.Xr bus_setup_intr 9 ,
871.Xr bus_teardown_intr 9 ,
872.Xr devclass 9 ,
873.Xr device 9 ,
874.Xr driver 9 ,
875.Xr rman 9
876.Rs
877.%B FreeBSD Developers' Handbook
878.%T NewBus
879.%U http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/developers-handbook/
880.Re
881.Rs
882.%A Shanley
883.%A Anderson
884.%B PCI System Architecture
885.%N 2nd Edition
886.%I Addison-Wesley
887.%O ISBN 0-201-30974-2
888.Re
889.Sh AUTHORS
890.An -nosplit
891This manual page was written by
892.An Bruce M Simpson Aq Mt bms@FreeBSD.org
893and
894.An John Baldwin Aq Mt jhb@FreeBSD.org .
895.Sh BUGS
896The kernel PCI code has a number of references to
897.Dq "slot numbers" .
898These do not refer to the geographic location of PCI devices,
899but to the device number assigned by the combination of the PCI IDSEL
900mechanism and the platform firmware.
901This should be taken note of when working with the kernel PCI code.
902.Pp
903The PCI bus driver should allocate the MSI-X vector table and PBA internally
904as necessary rather than requiring the caller to do so.
905