1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd January 8, 2020 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 11.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g., 72.Dv sparc64 , 73.Dv powerpc 74and AIM variants of 75.Dv powerpc64 , 76the kernel uses a separate address space. 77On other architectures, kernel and a user mode process share a 78single address space. 79The kernel is located at the highest addresses. 80.Pp 81On each architecture, the main user mode thread's stack starts near 82the highest user address and grows down. 83.Pp 84.Fx 85architecture support varies by release. 86This table shows the first 87.Fx 88release to support each architecture, and, for discontinued 89architectures, the final release. 90.Pp 91.Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release" 92.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 93.It aarch64 Ta 11.0 94.It alpha Ta 3.2 Ta 6.4 95.It amd64 Ta 5.1 96.It arm Ta 6.0 Ta 12.x 97.It armeb Ta 8.0 Ta 11.x 98.It armv6 Ta 10.0 99.It armv7 Ta 12.0 100.It ia64 Ta 5.0 Ta 10.4 101.It i386 Ta 1.0 102.It mips Ta 8.0 103.It mipsel Ta 9.0 104.It mipselhf Ta 12.0 105.It mipshf Ta 12.0 106.It mipsn32 Ta 9.0 107.It mips64 Ta 9.0 108.It mips64el Ta 9.0 109.It mips64elhf Ta 12.0 110.It mips64hf Ta 12.0 111.It pc98 Ta 2.2 Ta 11.x 112.It powerpc Ta 6.0 113.It powerpcspe Ta 12.0 114.It powerpc64 Ta 6.0 115.It riscv64 Ta 12.0 116.It riscv64sf Ta 12.0 117.It sparc64 Ta 5.0 Ta 12.x 118.El 119.Ss Type sizes 120All 121.Fx 122architectures use some variant of the ELF (see 123.Xr elf 5 ) 124.Sy Application Binary Interface 125(ABI) for the machine processor. 126All supported ABIs can be divided into two groups: 127.Bl -tag -width "Dv ILP32" 128.It Dv ILP32 129.Vt int , 130.Vt long , 131.Vt void * 132types machine representations all have 4-byte size. 133.It Dv LP64 134.Vt int 135type machine representation uses 4 bytes, 136while 137.Vt long 138and 139.Vt void * 140are 8 bytes. 141.El 142.Pp 143Some machines support more than one 144.Fx 145ABI. 146Typically these are 64-bit machines, where the 147.Dq native 148.Dv LP64 149execution environment is accompanied by the 150.Dq legacy 151.Dv ILP32 152environment, which was the historical 32-bit predecessor for 64-bit evolution. 153Examples are: 154.Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart" 155.It Sy LP64 Ta Sy ILP32 counterpart 156.It Dv amd64 Ta Dv i386 157.It Dv powerpc64 Ta Dv powerpc 158.It Dv mips64* Ta Dv mips* 159.It Dv aarch64 Ta Dv armv6/armv7 160.El 161.Pp 162.Dv aarch64 163will support execution of 164.Dv armv6 165or 166.Dv armv7 167binaries if the CPU implements 168.Dv AArch32 169execution state, however 170.Dv armv5 171binaries aren't supported. 172.Pp 173On all supported architectures: 174.Bl -column -offset -indent "long long" "Size" 175.It Sy Type Ta Sy Size 176.It short Ta 2 177.It int Ta 4 178.It long Ta sizeof(void*) 179.It long long Ta 8 180.It float Ta 4 181.It double Ta 8 182.El 183.Pp 184Integers are represented in two's complement. 185Alignment of integer and pointer types is natural, that is, 186the address of the variable must be congruent to zero modulo the type size. 187Most ILP32 ABIs, except 188.Dv arm , 189require only 4-byte alignment for 64-bit integers. 190.Pp 191Machine-dependent type sizes: 192.Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t" 193.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 194.It aarch64 Ta 8 Ta 16 Ta 8 195.It amd64 Ta 8 Ta 16 Ta 8 196.It armv6 Ta 4 Ta 8 Ta 8 197.It armv7 Ta 4 Ta 8 Ta 8 198.It i386 Ta 4 Ta 12 Ta 4 199.It mips Ta 4 Ta 8 Ta 8 200.It mipsel Ta 4 Ta 8 Ta 8 201.It mipselhf Ta 4 Ta 8 Ta 8 202.It mipshf Ta 4 Ta 8 Ta 8 203.It mipsn32 Ta 4 Ta 8 Ta 8 204.It mips64 Ta 8 Ta 8 Ta 8 205.It mips64el Ta 8 Ta 8 Ta 8 206.It mips64elhf Ta 8 Ta 8 Ta 8 207.It mips64hf Ta 8 Ta 8 Ta 8 208.It powerpc Ta 4 Ta 8 Ta 8 209.It powerpcspe Ta 4 Ta 8 Ta 8 210.It powerpc64 Ta 8 Ta 8 Ta 8 211.It riscv64 Ta 8 Ta 16 Ta 8 212.It riscv64sf Ta 8 Ta 16 Ta 8 213.It sparc64 Ta 8 Ta 16 Ta 8 214.El 215.Pp 216.Sy time_t 217is 8 bytes on all supported architectures except i386. 218.Ss Endianness and Char Signedness 219.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" 220.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 221.It aarch64 Ta little Ta unsigned 222.It amd64 Ta little Ta signed 223.It armv6 Ta little Ta unsigned 224.It armv7 Ta little Ta unsigned 225.It i386 Ta little Ta signed 226.It mips Ta big Ta signed 227.It mipsel Ta little Ta signed 228.It mipselhf Ta little Ta signed 229.It mipshf Ta big Ta signed 230.It mipsn32 Ta big Ta signed 231.It mips64 Ta big Ta signed 232.It mips64el Ta little Ta signed 233.It mips64elhf Ta little Ta signed 234.It mips64hf Ta big Ta signed 235.It powerpc Ta big Ta unsigned 236.It powerpcspe Ta big Ta unsigned 237.It powerpc64 Ta big Ta unsigned 238.It riscv64 Ta little Ta signed 239.It riscv64sf Ta little Ta signed 240.It sparc64 Ta big Ta signed 241.El 242.Ss Page Size 243.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" 244.It Sy Architecture Ta Sy Page Sizes 245.It aarch64 Ta 4K, 2M, 1G 246.It amd64 Ta 4K, 2M, 1G 247.It armv6 Ta 4K, 1M 248.It armv7 Ta 4K, 1M 249.It i386 Ta 4K, 2M (PAE), 4M 250.It mips Ta 4K 251.It mipsel Ta 4K 252.It mipselhf Ta 4K 253.It mipshf Ta 4K 254.It mipsn32 Ta 4K 255.It mips64 Ta 4K 256.It mips64el Ta 4K 257.It mips64elhf Ta 4K 258.It mips64hf Ta 4K 259.It powerpc Ta 4K 260.It powerpcspe Ta 4K 261.It powerpc64 Ta 4K 262.It riscv64 Ta 4K 263.It riscv64sf Ta 4K 264.It sparc64 Ta 8K 265.El 266.Ss Floating Point 267.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" 268.It Sy Architecture Ta Sy float, double Ta Sy long double 269.It aarch64 Ta hard Ta soft, quad precision 270.It amd64 Ta hard Ta hard, 80 bit 271.It armv6 Ta hard Ta hard, double precision 272.It armv7 Ta hard Ta hard, double precision 273.It i386 Ta hard Ta hard, 80 bit 274.It mips Ta soft Ta identical to double 275.It mipsel Ta soft Ta identical to double 276.It mipselhf Ta hard Ta identical to double 277.It mipshf Ta hard Ta identical to double 278.It mipsn32 Ta soft Ta identical to double 279.It mips64 Ta soft Ta identical to double 280.It mips64el Ta soft Ta identical to double 281.It mips64elhf Ta hard Ta identical to double 282.It mips64hf Ta hard Ta identical to double 283.It powerpc Ta hard Ta hard, double precision 284.It powerpcspe Ta hard Ta hard, double precision 285.It powerpc64 Ta hard Ta hard, double precision 286.It riscv64 Ta hard Ta hard, double precision 287.It riscv64sf Ta soft Ta soft, double precision 288.It sparc64 Ta hard Ta hard, quad precision 289.El 290.Ss Default Tool Chain 291.Fx uses a variety of tool chain components for the supported CPU 292architectures: 293.Xr clang 1 294and 295.Xr ld.lld 1 296provided by the base system, 297GNU 298.Xr gcc 1 299and Binutils 300.Xr ld 1 , 301or an external toolchain compiler and linker provided by a port or package. 302This table shows the default tool chain for each architecture. 303.Bl -column -offset indent "Sy Architecture" "Sy Compiler" "Sy Linker" 304.It Sy Architecture Ta Sy Compiler Ta Sy Linker 305.It aarch64 Ta Clang Ta lld 306.It amd64 Ta Clang Ta lld 307.It armv6 Ta Clang Ta lld 308.It armv7 Ta Clang Ta lld 309.It i386 Ta Clang Ta lld 310.It mips Ta GCC(1) Ta GNU ld(1) 311.It mipsel Ta GCC(1) Ta GNU ld(1) 312.It mipselhf Ta GCC(1) Ta GNU ld(1) 313.It mipshf Ta GCC(1) Ta GNU ld(1) 314.It mipsn32 Ta GCC(1) Ta GNU ld(1) 315.It mips64 Ta GCC(1) Ta GNU ld(1) 316.It mips64el Ta GCC(1) Ta GNU ld(1) 317.It mips64elhf Ta GCC(1) Ta GNU ld(1) 318.It mips64hf Ta GCC(1) Ta GNU ld(1) 319.It powerpc Ta Clang Ta GNU ld 2.17.50 320.It powerpcspe Ta Clang Ta GNU ld 2.17.50 321.It powerpc64 Ta Clang Ta lld 322.It riscv64 Ta Clang Ta lld 323.It riscv64sf Ta Clang Ta lld 324.It sparc64 Ta GCC(1) Ta GNU ld(1) 325.El 326.Pp 327(1) External toolchain provided by ports/packages. 328.Pp 329Note that GCC 4.2.1 is deprecated, and scheduled for removal on 2020-03-31. 330Any CPU architectures not migrated by then 331(to either base system Clang or external toolchain) 332may be removed from the tree after that date. 333make universe will not build mips or sparc64 334architectures unless the xtoolchain binaries have been installed for 335the architecture. 336.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE 337.Dv MACHINE_CPUARCH 338should be preferred in Makefiles when the generic 339architecture is being tested. 340.Dv MACHINE_ARCH 341should be preferred when there is something specific to a particular type of 342architecture where there is a choice of many, or could be a choice of many. 343Use 344.Dv MACHINE 345when referring to the kernel, interfaces dependent on a specific type of kernel 346or similar things like boot sequences. 347.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH" 348.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH 349.It arm64 Ta aarch64 Ta aarch64 350.It amd64 Ta amd64 Ta amd64 351.It arm Ta arm Ta armv6, armv7 352.It i386 Ta i386 Ta i386 353.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32 354.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64 355.It riscv Ta riscv Ta riscv64, riscv64sf 356.It sparc64 Ta sparc64 Ta sparc64 357.El 358.Ss Predefined Macros 359The compiler provides a number of predefined macros. 360Some of these provide architecture-specific details and are explained below. 361Other macros, including those required by the language standard, are not 362included here. 363.Pp 364The full set of predefined macros can be obtained with this command: 365.Bd -literal -offset indent 366cc -x c -dM -E /dev/null 367.Ed 368.Pp 369Common type size and endianness macros: 370.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning" 371.It Sy Macro Ta Sy Meaning 372.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 373.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 374.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 375.Dv PDP11_ENDIAN 376is not used on 377.Fx . 378.El 379.Pp 380Architecture-specific macros: 381.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" 382.It Sy Architecture Ta Sy Predefined macros 383.It aarch64 Ta Dv __aarch64__ 384.It amd64 Ta Dv __amd64__, Dv __x86_64__ 385.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 386.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7 387.It i386 Ta Dv __i386__ 388.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 389.It mipsel Ta Dv __mips__, Dv __mips_o32 390.It mipselhf Ta Dv __mips__, Dv __mips_o32 391.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 392.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 393.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 394.It mips64el Ta Dv __mips__, Dv __mips_n64 395.It mips64elhf Ta Dv __mips__, Dv __mips_n64 396.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 397.It powerpc Ta Dv __powerpc__ 398.It powerpcspe Ta Dv __powerpc__, Dv __SPE__ 399.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ 400.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 401.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 402.It sparc64 Ta Dv __sparc64__ 403.El 404.Pp 405Compilers may define additional variants of architecture-specific macros. 406The macros above are preferred for use in 407.Fx . 408.Ss Important Xr make 1 variables 409Most of the externally settable variables are defined in the 410.Xr build 7 411man page. 412These variables are not otherwise documented and are used extensively 413in the build system. 414.Bl -tag -width "MACHINE_CPUARCH" 415.It Dv MACHINE 416Represents the hardware platform. 417This is the same as the native platform's 418.Xr uname 1 419.Fl m 420output. 421It defines both the userland / kernel interface, as well as the 422bootloader / kernel interface. 423It should only be used in these contexts. 424Each CPU architecture may have multiple hardware platforms it supports 425where 426.Dv MACHINE 427differs among them. 428It is used to collect together all the files from 429.Xr config 8 430to build the kernel. 431It is often the same as 432.Dv MACHINE_ARCH 433just as one CPU architecture can be implemented by many different 434hardware platforms, one hardware platform may support multiple CPU 435architecture family members, though with different binaries. 436For example, 437.Dv MACHINE 438of i386 supported the IBM-AT hardware platform while the 439.Dv MACHINE 440of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 441hardware platforms. 442Both of these hardware platforms supported only the 443.Dv MACHINE_ARCH 444of i386 where they shared a common ABI, except for certain kernel / 445userland interfaces relating to underlying hardware platform 446differences in bus architecture, device enumeration and boot interface. 447Generally, 448.Dv MACHINE 449should only be used in src/sys and src/stand or in system imagers or 450installers. 451.It Dv MACHINE_ARCH 452Represents the CPU processor architecture. 453This is the same as the native platforms 454.Xr uname 1 455.Fl p 456output. 457It defines the CPU instruction family supported. 458It may also encode a variation in the byte ordering of multi-byte 459integers (endian). 460It may also encode a variation in the size of the integer or pointer. 461It may also encode a ISA revision. 462It may also encode hard versus soft floating point ABI and usage. 463It may also encode a variant ABI when the other factors do not 464uniquely define the ABI (e.g., MIPS' n32 ABI). 465It, along with 466.Dv MACHINE , 467defines the ABI used by the system. 468For example, the MIPS CPU processor family supports 9 different 469combinations encoding pointer size, endian and hard versus soft float (for 4708 combinations) as well as N32 (which only ever had one variation of 471all these). 472Generally, the plain CPU name specifies the most common (or at least 473first) variant of the CPU. 474This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7' 475imply little endian. 476If we ever were to support the so-called x32 ABI (using 32-bit 477pointers on the amd64 architecture), it would most likely be encoded 478as amd64-x32. 479It is unfortunate that amd64 specifies the 64-bit evolution of the x86 480platform (it matches the 'first rule') as everybody else uses x86_64. 481There is no standard name for the processor: each OS selects its own 482conventions. 483.It Dv MACHINE_CPUARCH 484Represents the source location for a given 485.Dv MACHINE_ARCH . 486It is generally the common prefix for all the MACHINE_ARCH that 487share the same implementation, though 'riscv' breaks this rule. 488For example, 489.Dv MACHINE_CPUARCH 490is defined to be mips for all the flavors of mips that we support 491since we support them all with a shared set of sources. 492While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 493for them. 494The FreeBSD source base supports amd64 and i386 with two 495distinct source bases living in subdirectories named amd64 and i386 496(though behind the scenes there's some sharing that fits into this 497framework). 498.It Dv CPUTYPE 499Sets the flavor of 500.Dv MACHINE_ARCH 501to build. 502It is used to optimize the build for a specific CPU / core that the 503binaries run on. 504Generally, this does not change the ABI, though it can be a fine line 505between optimization for specific cases. 506.It Dv TARGET 507Used to set 508.Dv MACHINE 509in the top level Makefile for cross building. 510Unused outside of that scope. 511It is not passed down to the rest of the build. 512Makefiles outside of the top level should not use it at all (though 513some have their own private copy for hysterical raisons). 514.It Dv TARGET_ARCH 515Used to set 516.Dv MACHINE_ARCH 517by the top level Makefile for cross building. 518Like 519.Dv TARGET , 520it is unused outside of that scope. 521.El 522.Sh SEE ALSO 523.Xr src.conf 5 , 524.Xr build 7 525.Sh HISTORY 526An 527.Nm 528manual page appeared in 529.Fx 11.1 . 530