1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd September 15, 2022 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 12.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g., 72.Dv powerpc 73and AIM variants of 74.Dv powerpc64 , 75the kernel uses a separate address space. 76On other architectures, kernel and a user mode process share a 77single address space. 78The kernel is located at the highest addresses. 79.Pp 80On each architecture, the main user mode thread's stack starts near 81the highest user address and grows down. 82.Pp 83.Fx 84architecture support varies by release. 85This table shows currently supported CPU architectures along with the first 86.Fx 87release to support each architecture. 88.Bl -column -offset indent "Architecture" "Initial Release" 89.It Sy Architecture Ta Sy Initial Release 90.It aarch64 Ta 11.0 91.It amd64 Ta 5.1 92.It armv6 Ta 10.0 93.It armv7 Ta 12.0 94.It i386 Ta 1.0 95.It powerpc Ta 6.0 96.It powerpcspe Ta 12.0 97.It powerpc64 Ta 9.0 98.It powerpc64le Ta 13.0 99.It riscv64 Ta 12.0 100.It riscv64sf Ta 12.0 101.El 102.Pp 103Discontinued architectures are shown in the following table. 104.Bl -column -offset indent "Architecture" "Initial Release" "Final Release" 105.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 106.It alpha Ta 3.2 Ta 6.4 107.It arm Ta 6.0 Ta 12.x 108.It armeb Ta 8.0 Ta 11.4 109.It ia64 Ta 5.0 Ta 10.4 110.It mips Ta 8.0 Ta 13.x 111.It mipsel Ta 9.0 Ta 13.x 112.It mipselhf Ta 12.0 Ta 13.x 113.It mipshf Ta 12.0 Ta 13.x 114.It mipsn32 Ta 9.0 Ta 13.x 115.It mips64 Ta 9.0 Ta 13.x 116.It mips64el Ta 9.0 Ta 13.x 117.It mips64elhf Ta 12.0 Ta 13.x 118.It mips64hf Ta 12.0 Ta 13.x 119.It pc98 Ta 2.2 Ta 11.4 120.It sparc64 Ta 5.0 Ta 12.x 121.El 122.Ss Type sizes 123All 124.Fx 125architectures use some variant of the ELF (see 126.Xr elf 5 ) 127.Sy Application Binary Interface 128(ABI) for the machine processor. 129All supported ABIs can be divided into two groups: 130.Bl -tag -width "Dv ILP32" 131.It Dv ILP32 132.Vt int , 133.Vt long , 134.Vt void * 135types machine representations all have 4-byte size. 136.It Dv LP64 137.Vt int 138type machine representation uses 4 bytes, 139while 140.Vt long 141and 142.Vt void * 143are 8 bytes. 144.El 145.Pp 146Some machines support more than one 147.Fx 148ABI. 149Typically these are 64-bit machines, where the 150.Dq native 151.Dv LP64 152execution environment is accompanied by the 153.Dq legacy 154.Dv ILP32 155environment, which was the historical 32-bit predecessor for 64-bit evolution. 156Examples are: 157.Bl -column -offset indent "powerpc64" "ILP32 counterpart" 158.It Sy LP64 Ta Sy ILP32 counterpart 159.It Dv amd64 Ta Dv i386 160.It Dv powerpc64 Ta Dv powerpc 161.It Dv mips64* Ta Dv mips* 162.It Dv aarch64 Ta Dv armv6/armv7 163.El 164.Pp 165.Dv aarch64 166will support execution of 167.Dv armv6 168or 169.Dv armv7 170binaries if the CPU implements 171.Dv AArch32 172execution state, however older 173.Dv armv4 174and 175.Dv armv5 176binaries aren't supported. 177.Pp 178On all supported architectures: 179.Bl -column -offset -indent "long long" "Size" 180.It Sy Type Ta Sy Size 181.It short Ta 2 182.It int Ta 4 183.It long Ta sizeof(void*) 184.It long long Ta 8 185.It float Ta 4 186.It double Ta 8 187.El 188.Pp 189Integers are represented in two's complement. 190Alignment of integer and pointer types is natural, that is, 191the address of the variable must be congruent to zero modulo the type size. 192Most ILP32 ABIs, except 193.Dv arm , 194require only 4-byte alignment for 64-bit integers. 195.Pp 196Machine-dependent type sizes: 197.Bl -column -offset indent "Architecture" "void *" "long double" "time_t" 198.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 199.It aarch64 Ta 8 Ta 16 Ta 8 200.It amd64 Ta 8 Ta 16 Ta 8 201.It armv6 Ta 4 Ta 8 Ta 8 202.It armv7 Ta 4 Ta 8 Ta 8 203.It i386 Ta 4 Ta 12 Ta 4 204.It mips Ta 4 Ta 8 Ta 8 205.It mipsel Ta 4 Ta 8 Ta 8 206.It mipselhf Ta 4 Ta 8 Ta 8 207.It mipshf Ta 4 Ta 8 Ta 8 208.It mipsn32 Ta 4 Ta 8 Ta 8 209.It mips64 Ta 8 Ta 8 Ta 8 210.It mips64el Ta 8 Ta 8 Ta 8 211.It mips64elhf Ta 8 Ta 8 Ta 8 212.It mips64hf Ta 8 Ta 8 Ta 8 213.It powerpc Ta 4 Ta 8 Ta 8 214.It powerpcspe Ta 4 Ta 8 Ta 8 215.It powerpc64 Ta 8 Ta 8 Ta 8 216.It powerpc64le Ta 8 Ta 8 Ta 8 217.It riscv64 Ta 8 Ta 16 Ta 8 218.It riscv64sf Ta 8 Ta 16 Ta 8 219.El 220.Pp 221.Sy time_t 222is 8 bytes on all supported architectures except i386. 223.Ss Endianness and Char Signedness 224.Bl -column -offset indent "Architecture" "Endianness" "char Signedness" 225.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 226.It aarch64 Ta little Ta unsigned 227.It amd64 Ta little Ta signed 228.It armv6 Ta little Ta unsigned 229.It armv7 Ta little Ta unsigned 230.It i386 Ta little Ta signed 231.It mips Ta big Ta signed 232.It mipsel Ta little Ta signed 233.It mipselhf Ta little Ta signed 234.It mipshf Ta big Ta signed 235.It mipsn32 Ta big Ta signed 236.It mips64 Ta big Ta signed 237.It mips64el Ta little Ta signed 238.It mips64elhf Ta little Ta signed 239.It mips64hf Ta big Ta signed 240.It powerpc Ta big Ta unsigned 241.It powerpcspe Ta big Ta unsigned 242.It powerpc64 Ta big Ta unsigned 243.It powerpc64le Ta little Ta unsigned 244.It riscv64 Ta little Ta signed 245.It riscv64sf Ta little Ta signed 246.El 247.Ss Page Size 248.Bl -column -offset indent "Architecture" "Page Sizes" 249.It Sy Architecture Ta Sy Page Sizes 250.It aarch64 Ta 4K, 2M, 1G 251.It amd64 Ta 4K, 2M, 1G 252.It armv6 Ta 4K, 1M 253.It armv7 Ta 4K, 1M 254.It i386 Ta 4K, 2M (PAE), 4M 255.It mips Ta 4K 256.It mipsel Ta 4K 257.It mipselhf Ta 4K 258.It mipshf Ta 4K 259.It mipsn32 Ta 4K 260.It mips64 Ta 4K 261.It mips64el Ta 4K 262.It mips64elhf Ta 4K 263.It mips64hf Ta 4K 264.It powerpc Ta 4K 265.It powerpcspe Ta 4K 266.It powerpc64 Ta 4K 267.It powerpc64le Ta 4K 268.It riscv64 Ta 4K, 2M, 1G 269.It riscv64sf Ta 4K, 2M, 1G 270.El 271.Ss Floating Point 272.Bl -column -offset indent "Architecture" "float, double" "long double" 273.It Sy Architecture Ta Sy float, double Ta Sy long double 274.It aarch64 Ta hard Ta soft, quad precision 275.It amd64 Ta hard Ta hard, 80 bit 276.It armv6 Ta hard Ta hard, double precision 277.It armv7 Ta hard Ta hard, double precision 278.It i386 Ta hard Ta hard, 80 bit 279.It mips Ta soft Ta identical to double 280.It mipsel Ta soft Ta identical to double 281.It mipselhf Ta hard Ta identical to double 282.It mipshf Ta hard Ta identical to double 283.It mipsn32 Ta soft Ta identical to double 284.It mips64 Ta soft Ta identical to double 285.It mips64el Ta soft Ta identical to double 286.It mips64elhf Ta hard Ta identical to double 287.It mips64hf Ta hard Ta identical to double 288.It powerpc Ta hard Ta hard, double precision 289.It powerpcspe Ta hard Ta hard, double precision 290.It powerpc64 Ta hard Ta hard, double precision 291.It powerpc64le Ta hard Ta hard, double precision 292.It riscv64 Ta hard Ta hard, quad precision 293.It riscv64sf Ta soft Ta soft, quad precision 294.El 295.Ss Default Tool Chain 296.Fx 297uses 298.Xr clang 1 299as the default compiler on all supported CPU architectures, 300LLVM's 301.Xr ld.lld 1 302as the default linker, and 303ELF Tool Chain binary utilities such as 304.Xr objcopy 1 305and 306.Xr readelf 1 . 307.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE 308.Dv MACHINE_CPUARCH 309should be preferred in Makefiles when the generic 310architecture is being tested. 311.Dv MACHINE_ARCH 312should be preferred when there is something specific to a particular type of 313architecture where there is a choice of many, or could be a choice of many. 314Use 315.Dv MACHINE 316when referring to the kernel, interfaces dependent on a specific type of kernel 317or similar things like boot sequences. 318.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH" 319.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH 320.It arm64 Ta aarch64 Ta aarch64 321.It amd64 Ta amd64 Ta amd64 322.It arm Ta arm Ta armv6, armv7 323.It i386 Ta i386 Ta i386 324.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32 325.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le 326.It riscv Ta riscv Ta riscv64, riscv64sf 327.El 328.Ss Predefined Macros 329The compiler provides a number of predefined macros. 330Some of these provide architecture-specific details and are explained below. 331Other macros, including those required by the language standard, are not 332included here. 333.Pp 334The full set of predefined macros can be obtained with this command: 335.Bd -literal -offset indent 336cc -x c -dM -E /dev/null 337.Ed 338.Pp 339Common type size and endianness macros: 340.Bl -column -offset indent "BYTE_ORDER" "Meaning" 341.It Sy Macro Ta Sy Meaning 342.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 343.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 344.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 345.Dv PDP11_ENDIAN 346is not used on 347.Fx . 348.El 349.Pp 350Architecture-specific macros: 351.Bl -column -offset indent "Architecture" "Predefined macros" 352.It Sy Architecture Ta Sy Predefined macros 353.It aarch64 Ta Dv __aarch64__ 354.It amd64 Ta Dv __amd64__ , Dv __x86_64__ 355.It armv6 Ta Dv __arm__ , Dv __ARM_ARCH >= 6 356.It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7 357.It i386 Ta Dv __i386__ 358.It mips Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32 359.It mipsel Ta Dv __mips__ , Dv __mips_o32 360.It mipselhf Ta Dv __mips__ , Dv __mips_o32 361.It mipshf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32 362.It mipsn32 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n32 363.It mips64 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64 364.It mips64el Ta Dv __mips__ , Dv __mips_n64 365.It mips64elhf Ta Dv __mips__ , Dv __mips_n64 366.It mips64hf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64 367.It powerpc Ta Dv __powerpc__ 368.It powerpcspe Ta Dv __powerpc__ , Dv __SPE__ 369.It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__ 370.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__ 371.It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64 372.It riscv64sf Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __riscv_float_abi_soft 373.El 374.Pp 375Compilers may define additional variants of architecture-specific macros. 376The macros above are preferred for use in 377.Fx . 378.Ss Important Xr make 1 variables 379Most of the externally settable variables are defined in the 380.Xr build 7 381man page. 382These variables are not otherwise documented and are used extensively 383in the build system. 384.Bl -tag -width "MACHINE_CPUARCH" 385.It Dv MACHINE 386Represents the hardware platform. 387This is the same as the native platform's 388.Xr uname 1 389.Fl m 390output. 391It defines both the userland / kernel interface, as well as the 392bootloader / kernel interface. 393It should only be used in these contexts. 394Each CPU architecture may have multiple hardware platforms it supports 395where 396.Dv MACHINE 397differs among them. 398It is used to collect together all the files from 399.Xr config 8 400to build the kernel. 401It is often the same as 402.Dv MACHINE_ARCH 403just as one CPU architecture can be implemented by many different 404hardware platforms, one hardware platform may support multiple CPU 405architecture family members, though with different binaries. 406For example, 407.Dv MACHINE 408of i386 supported the IBM-AT hardware platform while the 409.Dv MACHINE 410of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 411hardware platforms. 412Both of these hardware platforms supported only the 413.Dv MACHINE_ARCH 414of i386 where they shared a common ABI, except for certain kernel / 415userland interfaces relating to underlying hardware platform 416differences in bus architecture, device enumeration and boot interface. 417Generally, 418.Dv MACHINE 419should only be used in src/sys and src/stand or in system imagers or 420installers. 421.It Dv MACHINE_ARCH 422Represents the CPU processor architecture. 423This is the same as the native platforms 424.Xr uname 1 425.Fl p 426output. 427It defines the CPU instruction family supported. 428It may also encode a variation in the byte ordering of multi-byte 429integers (endian). 430It may also encode a variation in the size of the integer or pointer. 431It may also encode a ISA revision. 432It may also encode hard versus soft floating point ABI and usage. 433It may also encode a variant ABI when the other factors do not 434uniquely define the ABI (e.g., MIPS' n32 ABI). 435It, along with 436.Dv MACHINE , 437defines the ABI used by the system. 438For example, the MIPS CPU processor family supports 9 different 439combinations encoding pointer size, endian and hard versus soft float (for 4408 combinations) as well as N32 (which only ever had one variation of 441all these). 442Generally, the plain CPU name specifies the most common (or at least 443first) variant of the CPU. 444This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7' 445imply little endian. 446If we ever were to support the so-called x32 ABI (using 32-bit 447pointers on the amd64 architecture), it would most likely be encoded 448as amd64-x32. 449It is unfortunate that amd64 specifies the 64-bit evolution of the x86 450platform (it matches the 'first rule') as everybody else uses x86_64. 451There is no standard name for the processor: each OS selects its own 452conventions. 453.It Dv MACHINE_CPUARCH 454Represents the source location for a given 455.Dv MACHINE_ARCH . 456It is generally the common prefix for all the MACHINE_ARCH that 457share the same implementation, though 'riscv' breaks this rule. 458For example, 459.Dv MACHINE_CPUARCH 460is defined to be mips for all the flavors of mips that we support 461since we support them all with a shared set of sources. 462While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 463for them. 464The 465.Fx 466source base supports amd64 and i386 with two 467distinct source bases living in subdirectories named amd64 and i386 468(though behind the scenes there's some sharing that fits into this 469framework). 470.It Dv CPUTYPE 471Sets the flavor of 472.Dv MACHINE_ARCH 473to build. 474It is used to optimize the build for a specific CPU / core that the 475binaries run on. 476Generally, this does not change the ABI, though it can be a fine line 477between optimization for specific cases. 478.It Dv TARGET 479Used to set 480.Dv MACHINE 481in the top level Makefile for cross building. 482Unused outside of that scope. 483It is not passed down to the rest of the build. 484Makefiles outside of the top level should not use it at all (though 485some have their own private copy for hysterical raisons). 486.It Dv TARGET_ARCH 487Used to set 488.Dv MACHINE_ARCH 489by the top level Makefile for cross building. 490Like 491.Dv TARGET , 492it is unused outside of that scope. 493.El 494.Sh SEE ALSO 495.Xr src.conf 5 , 496.Xr build 7 497.Sh HISTORY 498An 499.Nm 500manual page appeared in 501.Fx 11.1 . 502