1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd November 20, 2019 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 11.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g., 72.Dv sparc64 , 73.Dv powerpc 74and AIM variants of 75.Dv powerpc64 , 76the kernel uses a separate address space. 77On other architectures, kernel and a user mode process share a 78single address space. 79The kernel is located at the highest addresses. 80.Pp 81On each architecture, the main user mode thread's stack starts near 82the highest user address and grows down. 83.Pp 84.Fx 85architecture support varies by release. 86This table shows the first 87.Fx 88release to support each architecture, and, for discontinued 89architectures, the final release. 90.Pp 91.Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release" 92.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 93.It aarch64 Ta 11.0 94.It alpha Ta 3.2 Ta 6.4 95.It amd64 Ta 5.1 96.It arm Ta 6.0 Ta 12.x 97.It armeb Ta 8.0 Ta 11.x 98.It armv6 Ta 10.0 99.It armv7 Ta 12.0 100.It ia64 Ta 5.0 Ta 10.4 101.It i386 Ta 1.0 102.It mips Ta 8.0 103.It mipsel Ta 9.0 104.It mipselhf Ta 12.0 105.It mipshf Ta 12.0 106.It mipsn32 Ta 9.0 107.It mips64 Ta 9.0 108.It mips64el Ta 9.0 109.It mips64elhf Ta 12.0 110.It mips64hf Ta 12.0 111.It pc98 Ta 2.2 Ta 11.x 112.It powerpc Ta 6.0 113.It powerpcspe Ta 12.0 114.It powerpc64 Ta 6.0 115.It riscv64 Ta 12.0 116.It riscv64sf Ta 12.0 117.It sparc64 Ta 5.0 Ta 12.x 118.El 119.Ss Type sizes 120All 121.Fx 122architectures use some variant of the ELF (see 123.Xr elf 5 ) 124.Sy Application Binary Interface 125(ABI) for the machine processor. 126All supported ABIs can be divided into two groups: 127.Bl -tag -width "Dv ILP32" 128.It Dv ILP32 129.Vt int , 130.Vt long , 131.Vt void * 132types machine representations all have 4-byte size. 133.It Dv LP64 134.Vt int 135type machine representation uses 4 bytes, 136while 137.Vt long 138and 139.Vt void * 140are 8 bytes. 141.El 142.Pp 143Compilers define the 144.Dv _LP64 145symbol when compiling for an 146.Dv LP64 147ABI. 148.Pp 149Some machines support more than one 150.Fx 151ABI. 152Typically these are 64-bit machines, where the 153.Dq native 154.Dv LP64 155execution environment is accompanied by the 156.Dq legacy 157.Dv ILP32 158environment, which was the historical 32-bit predecessor for 64-bit evolution. 159Examples are: 160.Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart" 161.It Sy LP64 Ta Sy ILP32 counterpart 162.It Dv amd64 Ta Dv i386 163.It Dv powerpc64 Ta Dv powerpc 164.It Dv mips64* Ta Dv mips* 165.It Dv aarch64 Ta Dv armv6/armv7 166.El 167.Pp 168.Dv aarch64 169will support execution of 170.Dv armv6 171or 172.Dv armv7 173binaries if the CPU implements 174.Dv AArch32 175execution state, however 176.Dv armv5 177binaries aren't supported. 178.Pp 179On all supported architectures: 180.Bl -column -offset -indent "long long" "Size" 181.It Sy Type Ta Sy Size 182.It short Ta 2 183.It int Ta 4 184.It long Ta sizeof(void*) 185.It long long Ta 8 186.It float Ta 4 187.It double Ta 8 188.El 189.Pp 190Integers are represented in two's complement. 191Alignment of integer and pointer types is natural, that is, 192the address of the variable must be congruent to zero modulo the type size. 193Most ILP32 ABIs, except 194.Dv arm , 195require only 4-byte alignment for 64-bit integers. 196.Pp 197Machine-dependent type sizes: 198.Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t" 199.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 200.It aarch64 Ta 8 Ta 16 Ta 8 201.It amd64 Ta 8 Ta 16 Ta 8 202.It arm Ta 4 Ta 8 Ta 8 203.It armv6 Ta 4 Ta 8 Ta 8 204.It i386 Ta 4 Ta 12 Ta 4 205.It mips Ta 4 Ta 8 Ta 8 206.It mipsel Ta 4 Ta 8 Ta 8 207.It mipselhf Ta 4 Ta 8 Ta 8 208.It mipshf Ta 4 Ta 8 Ta 8 209.It mipsn32 Ta 4 Ta 8 Ta 8 210.It mips64 Ta 8 Ta 8 Ta 8 211.It mips64el Ta 8 Ta 8 Ta 8 212.It mips64elhf Ta 8 Ta 8 Ta 8 213.It mips64hf Ta 8 Ta 8 Ta 8 214.It powerpc Ta 4 Ta 8 Ta 8 215.It powerpcspe Ta 4 Ta 8 Ta 8 216.It powerpc64 Ta 8 Ta 8 Ta 8 217.It riscv64 Ta 8 Ta 16 Ta 8 218.It riscv64sf Ta 8 Ta 16 Ta 8 219.It sparc64 Ta 8 Ta 16 Ta 8 220.El 221.Pp 222.Sy time_t 223is 8 bytes on all supported architectures except i386. 224.Ss Endianness and Char Signedness 225.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" 226.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 227.It aarch64 Ta little Ta unsigned 228.It amd64 Ta little Ta signed 229.It arm Ta little Ta unsigned 230.It armv6 Ta little Ta unsigned 231.It armv7 Ta little Ta unsigned 232.It i386 Ta little Ta signed 233.It mips Ta big Ta signed 234.It mipsel Ta little Ta signed 235.It mipselhf Ta little Ta signed 236.It mipshf Ta big Ta signed 237.It mipsn32 Ta big Ta signed 238.It mips64 Ta big Ta signed 239.It mips64el Ta little Ta signed 240.It mips64elhf Ta little Ta signed 241.It mips64hf Ta big Ta signed 242.It powerpc Ta big Ta unsigned 243.It powerpcspe Ta big Ta unsigned 244.It powerpc64 Ta big Ta unsigned 245.It riscv64 Ta little Ta signed 246.It riscv64sf Ta little Ta signed 247.It sparc64 Ta big Ta signed 248.El 249.Ss Page Size 250.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" 251.It Sy Architecture Ta Sy Page Sizes 252.It aarch64 Ta 4K, 2M, 1G 253.It amd64 Ta 4K, 2M, 1G 254.It arm Ta 4K 255.It armv6 Ta 4K, 1M 256.It armv7 Ta 4K, 1M 257.It i386 Ta 4K, 2M (PAE), 4M 258.It mips Ta 4K 259.It mipsel Ta 4K 260.It mipselhf Ta 4K 261.It mipshf Ta 4K 262.It mipsn32 Ta 4K 263.It mips64 Ta 4K 264.It mips64el Ta 4K 265.It mips64elhf Ta 4K 266.It mips64hf Ta 4K 267.It powerpc Ta 4K 268.It powerpcspe Ta 4K 269.It powerpc64 Ta 4K 270.It riscv64 Ta 4K 271.It riscv64sf Ta 4K 272.It sparc64 Ta 8K 273.El 274.Ss Floating Point 275.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" 276.It Sy Architecture Ta Sy float, double Ta Sy long double 277.It aarch64 Ta hard Ta soft, quad precision 278.It amd64 Ta hard Ta hard, 80 bit 279.It arm Ta soft Ta soft, double precision 280.It armv6 Ta hard Ta hard, double precision 281.It armv7 Ta hard Ta hard, double precision 282.It i386 Ta hard Ta hard, 80 bit 283.It mips Ta soft Ta identical to double 284.It mipsel Ta soft Ta identical to double 285.It mipselhf Ta hard Ta identical to double 286.It mipshf Ta hard Ta identical to double 287.It mipsn32 Ta soft Ta identical to double 288.It mips64 Ta soft Ta identical to double 289.It mips64el Ta soft Ta identical to double 290.It mips64elhf Ta hard Ta identical to double 291.It mips64hf Ta hard Ta identical to double 292.It powerpc Ta hard Ta hard, double precision 293.It powerpcspe Ta hard Ta hard, double precision 294.It powerpc64 Ta hard Ta hard, double precision 295.It riscv64 Ta hard Ta hard, double precision 296.It riscv64sf Ta soft Ta soft, double precision 297.It sparc64 Ta hard Ta hard, quad precision 298.El 299.Ss Default Tool Chain 300.Fx uses a variety of tool chain components for the supported CPU 301architectures: 302.Xr clang 1 303and 304.Xr ld.lld 1 305provided by the base system, 306GNU 307.Xr gcc 1 308and Binutils 309.Xr ld 1 , 310or an external toolchain compiler and linker provided by a port or package. 311This table shows the default tool chain for each architecture. 312.Bl -column -offset indent "Sy Architecture" "Sy Compiler" "Sy Linker" 313.It Sy Architecture Ta Sy Compiler Ta Sy Linker 314.It aarch64 Ta Clang Ta lld 315.It amd64 Ta Clang Ta lld 316.It arm Ta Clang Ta GNU ld 2.17.50 317.It armv6 Ta Clang Ta lld 318.It armv7 Ta Clang Ta lld 319.It i386 Ta Clang Ta lld 320.It mips Ta GCC 4.2.1 Ta GNU ld 2.17.50 321.It mipsel Ta GCC 4.2.1 Ta GNU ld 2.17.50 322.It mipselhf Ta GCC 4.2.1 Ta GNU ld 2.17.50 323.It mipshf Ta GCC 4.2.1 Ta GNU ld 2.17.50 324.It mipsn32 Ta GCC 4.2.1 Ta GNU ld 2.17.50 325.It mips64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 326.It mips64el Ta GCC 4.2.1 Ta GNU ld 2.17.50 327.It mips64elhf Ta GCC 4.2.1 Ta GNU ld 2.17.50 328.It mips64hf Ta GCC 4.2.1 Ta GNU ld 2.17.50 329.It powerpc Ta Clang Ta GNU ld 2.17.50 330.It powerpcspe Ta Clang Ta GNU ld 2.17.50 331.It powerpc64 Ta Clang Ta lld 332.It riscv64 Ta GCC(1) Ta GNU ld(1) 333.It riscv64sf Ta GCC(1) Ta GNU ld(1) 334.It sparc64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 335.El 336.Pp 337(1) External toolchain provided by ports/packages. 338.Pp 339Note that GCC 4.2.1 is deprecated, and scheduled for removal on 2020-03-31. 340Any CPU architectures not migrated by then 341(to either base system Clang or external toolchain) 342may be removed from the tree after that date. 343Unless the make variable 344.Dv MAKE_OBSOLETE_GCC 345is defined, make universe will not build mips or sparc64 346architectures unless the xtoolchain binaries have been installed for 347the architecture. 348.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE 349.Dv MACHINE_CPUARCH 350should be preferred in Makefiles when the generic 351architecture is being tested. 352.Dv MACHINE_ARCH 353should be preferred when there is something specific to a particular type of 354architecture where there is a choice of many, or could be a choice of many. 355Use 356.Dv MACHINE 357when referring to the kernel, interfaces dependent on a specific type of kernel 358or similar things like boot sequences. 359.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH" 360.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH 361.It arm64 Ta aarch64 Ta aarch64 362.It amd64 Ta amd64 Ta amd64 363.It arm Ta arm Ta arm, armv6, armv7 364.It i386 Ta i386 Ta i386 365.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32 366.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64 367.It riscv Ta riscv Ta riscv64, riscv64sf 368.It sparc64 Ta sparc64 Ta sparc64 369.El 370.Ss Predefined Macros 371The compiler provides a number of predefined macros. 372Some of these provide architecture-specific details and are explained below. 373Other macros, including those required by the language standard, are not 374included here. 375.Pp 376The full set of predefined macros can be obtained with this command: 377.Bd -literal -offset indent 378cc -x c -dM -E /dev/null 379.Ed 380.Pp 381Common type size and endianness macros: 382.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning" 383.It Sy Macro Ta Sy Meaning 384.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 385.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 386.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 387.Dv PDP11_ENDIAN 388is not used on 389.Fx . 390.El 391.Pp 392Architecture-specific macros: 393.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" 394.It Sy Architecture Ta Sy Predefined macros 395.It aarch64 Ta Dv __aarch64__ 396.It amd64 Ta Dv __amd64__, Dv __x86_64__ 397.It arm Ta Dv __arm__ 398.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 399.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7 400.It i386 Ta Dv __i386__ 401.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 402.It mipsel Ta Dv __mips__, Dv __mips_o32 403.It mipselhf Ta Dv __mips__, Dv __mips_o32 404.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 405.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 406.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 407.It mips64el Ta Dv __mips__, Dv __mips_n64 408.It mips64elhf Ta Dv __mips__, Dv __mips_n64 409.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 410.It powerpc Ta Dv __powerpc__ 411.It powerpcspe Ta Dv __powerpc__, Dv __SPE__ 412.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ 413.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 414.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 415.It sparc64 Ta Dv __sparc64__ 416.El 417.Pp 418Compilers may define additional variants of architecture-specific macros. 419The macros above are preferred for use in 420.Fx . 421.Ss Important Xr make 1 variables 422Most of the externally settable variables are defined in the 423.Xr build 7 424man page. 425These variables are not otherwise documented and are used extensively 426in the build system. 427.Bl -tag -width "MACHINE_CPUARCH" 428.It Dv MACHINE 429Represent the hardware platform. 430This is the same as the native platform's 431.Xr uname 1 432.Fl m 433output. 434It defines both the userland / kernel interface, as well as the 435bootloader / kernel interface. 436It should only be used in these contexts. 437Each CPU architecture may have multiple hardware platforms it supports 438where 439.Dv MACHINE 440differs among them. 441It is used to collect together all the files from 442.Xr config 8 443to build the kernel. 444It is often the same as 445.Dv MACHINE_ARCH 446just as one CPU architecture can be implemented by many different 447hardware platforms, one hardware platform may support multiple CPU 448architecture family members, though with different binaries. 449For example, 450.Dv MACHINE 451of i386 supported the IBM-AT hardware platform while the 452.Dv MACHINE 453of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 454hardware platforms. 455Both of these hardware platforms supported only the 456.Dv MACHINE_ARCH 457of i386 where they shared a common ABI, except for certain kernel / 458userland interfaces relating to underlying hardware platform 459differences in bus architecture, device enumeration and boot interface. 460Generally, 461.Dv MACHINE 462should only be used in src/sys and src/stand or in system imagers or 463installers. 464.It Dv MACHINE_ARCH 465Represents the CPU processor architecture. 466This is the same as the native platforms 467.Xr uname 1 468.Fl p 469output. 470It defines the CPU instruction family supported. 471It may also encode a variation in the byte ordering of multi-byte 472integers (endian). 473It may also encode a variation in the size of the integer or pointer. 474It may also encode a ISA revision. 475It may also encode hard versus soft floating point ABI and usage. 476It may also encode a variant ABI when the other factors do not 477uniquely define the ABI (e.g., MIPS' n32 ABI). 478It, along with 479.Dv MACHINE , 480defines the ABI used by the system. 481For example, the MIPS CPU processor family supports 9 different 482combinations encoding pointer size, endian and hard versus soft float (for 4838 combinations) as well as N32 (which only ever had one variation of 484all these). 485Generally, the plain CPU name specifies the most common (or at least 486first) variant of the CPU. 487This is why mips and mips64 imply 'big endian' while 'arm' and 'armv7' 488imply little endian. 489If we ever were to support the so-called x32 ABI (using 32-bit 490pointers on the amd64 architecture), it would most likely be encoded 491as amd64-x32. 492It is unfortunate that amd64 specifies the 64-bit evolution of the x86 493platform (it matches the 'first rule') as everybody else uses x86_64. 494There is no standard name for the processor: each OS selects its own 495conventions. 496.It Dv MACHINE_CPUARCH 497Represents the source location for a given 498.Dv MACHINE_ARCH . 499It is generally the common prefix for all the MACHINE_ARCH that 500share the same implementation, though 'riscv' breaks this rule. 501For example, 502.Dv MACHINE_CPUARCH 503is defined to be mips for all the flavors of mips that we support 504since we support them all with a shared set of sources. 505While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 506for them. 507The FreeBSD source base supports amd64 and i386 with two 508distinct source bases living in subdirectories named amd64 and i386 509(though behind the scenes there's some sharing that fits into this 510framework). 511.It Dv CPUTYPE 512Sets the flavor of 513.Dv MACHINE_ARCH 514to build. 515It is used to optimize the build for a specific CPU / core that the 516binaries run on. 517Generally, this does not change the ABI, though it can be a fine line 518between optimization for specific cases. 519.It Dv TARGET 520Used to set 521.Dv MACHINE 522in the top level Makefile for cross building. 523Unused outside of that scope. 524It is not passed down to the rest of the build. 525Makefiles outside of the top level should not use it at all (though 526some have their own private copy for hysterical raisons). 527.It Dv TARGET_ARCH 528Used to set 529.Dv MACHINE_ARCH 530by the top level Makefile for cross building. 531Like 532.Dv TARGET , 533it is unused outside of that scope. 534.El 535.Sh SEE ALSO 536.Xr src.conf 5 , 537.Xr build 7 538.Sh HISTORY 539An 540.Nm 541manual page appeared in 542.Fx 11.1 . 543