1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd May 16, 2017 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 10.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g. 72.Dv sparc64 , 73.Dv powerpc 74and AIM variants of 75.Dv powerpc64 , 76the kernel uses a separate address space. 77On other architectures, kernel and a user mode process share a 78single address space. 79The kernel is located at the highest addresses. 80.Pp 81On each architecture, the main user mode thread's stack starts near 82the highest user address and grows down. 83.Pp 84.Fx 85architecture support varies by release. 86This table shows the first 87.Fx 88release to support each architecture, and, for discontinued 89architectures, the final release. 90.Pp 91.Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release" 92.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 93.It alpha Ta 3.2 Ta 6.4 94.It amd64 Ta 5.1 95.It arm Ta 6.0 96.It armeb Ta 8.0 97.It armv6 Ta 10.0 98.It arm64 Ta 11.0 99.It ia64 Ta 5.0 Ta 10.x 100.It i386 Ta 1.0 101.It mips Ta 8.0 102.It mipsel Ta 9.0 103.It mipselhf Ta 12.0 104.It mipshf Ta 12.0 105.It mipsn32 Ta 9.0 106.It mips64 Ta 9.0 107.It mips64el Ta 9.0 108.It mips64elhf Ta 12.0 109.It mips64hf Ta 12.0 110.It pc98 Ta 2.2 Ta 11.x 111.It powerpc Ta 6.0 112.It powerpcspe Ta 12.0 113.It powerpc64 Ta 6.0 114.It riscv64 Ta 12.0 115.It riscv64sf Ta 12.0 116.It sparc64 Ta 5.0 117.El 118.Ss Type sizes 119All 120.Fx 121architectures use some variant of the ELF (see 122.Xr elf 5 ) 123.Sy Application Binary Interface 124(ABI) for the machine processor. 125All supported ABIs can be divided into two groups: 126.Bl -tag -width "Dv ILP32" 127.It Dv ILP32 128.Vt int , 129.Vt long , 130.Vt void * 131types machine representations all have 4-byte size. 132.It Dv LP64 133.Vt int 134type machine representation uses 4 bytes, 135while 136.Vt long 137and 138.Vt void * 139are 8 bytes. 140.El 141Compilers define the 142.Dv _LP64 143symbol when compiling for an 144.Dv LP64 145ABI. 146.Pp 147Some machines support more that one 148.Fx 149ABI. 150Typically these are 64-bit machines, where the 151.Dq native 152.Dv LP64 153execution environment is accompanied by the 154.Dq legacy 155.Dv ILP32 156environment, which was historical 32-bit predecessor for 64-bit evolution. 157Examples are: 158.Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart" 159.It Sy LP64 Ta Sy ILP32 counterpart 160.It Dv amd64 Ta Dv i386 161.It Dv powerpc64 Ta Dv powerpc 162.It Dv mips64* Ta Dv mips* 163.El 164.Dv arm64 165currently does not support execution of 166.Dv armv6 167binaries, even if the CPU implements 168.Dv AArch32 169execution state. 170.Pp 171On all supported architectures: 172.Bl -column -offset -indent "long long" "Size" 173.It Sy Type Ta Sy Size 174.It short Ta 2 175.It int Ta 4 176.It long Ta sizeof(void*) 177.It long long Ta 8 178.It float Ta 4 179.It double Ta 8 180.El 181Integers are represented in two's complement. 182Alignment of integer and pointer types is natural, that is, 183the address of the variable must be congruent to zero modulo the type size. 184Most ILP32 ABIs, except 185.Dv arm , 186require only 4-byte alignment for 64-bit integers. 187.Pp 188Machine-dependent type sizes: 189.Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t" 190.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 191.It amd64 Ta 8 Ta 16 Ta 8 192.It arm Ta 4 Ta 8 Ta 8 193.It armeb Ta 4 Ta 8 Ta 8 194.It armv6 Ta 4 Ta 8 Ta 8 195.It arm64 Ta 8 Ta 16 Ta 8 196.It i386 Ta 4 Ta 12 Ta 4 197.It mips Ta 4 Ta 8 Ta 8 198.It mipsel Ta 4 Ta 8 Ta 8 199.It mipselhf Ta 4 Ta 8 Ta 8 200.It mipshf Ta 4 Ta 8 Ta 8 201.It mipsn32 Ta 4 Ta 8 Ta 8 202.It mips64 Ta 8 Ta 8 Ta 8 203.It mips64el Ta 8 Ta 8 Ta 8 204.It mips64elhf Ta 8 Ta 8 Ta 8 205.It mips64hf Ta 8 Ta 8 Ta 8 206.It powerpc Ta 4 Ta 8 Ta 4 207.It powerpcspe Ta 4 Ta 8 Ta 4 208.It powerpc64 Ta 8 Ta 8 Ta 8 209.It riscv64 Ta 8 Ta 16 Ta 8 210.It riscv64sf Ta 8 Ta 16 Ta 8 211.It sparc64 Ta 8 Ta 16 Ta 8 212.El 213.Pp 214.Sy time_t 215is 8 bytes on all supported architectures except i386 and 32-bit 216variants of powerpc. 217.Ss Endianness and Char Signedness 218.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" 219.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 220.It amd64 Ta little Ta signed 221.It arm Ta little Ta unsigned 222.It armeb Ta big Ta unsigned 223.It armv6 Ta little Ta unsigned 224.It arm64 Ta little Ta unsigned 225.It i386 Ta little Ta signed 226.It mips Ta big Ta signed 227.It mipsel Ta little Ta signed 228.It mipselhf Ta little Ta signed 229.It mipshf Ta big Ta signed 230.It mipsn32 Ta big Ta signed 231.It mips64 Ta big Ta signed 232.It mips64el Ta little Ta signed 233.It mips64elhf Ta little Ta signed 234.It mips64hf Ta big Ta signed 235.It powerpc Ta big Ta unsigned 236.It powerpcspe Ta big Ta unsigned 237.It powerpc64 Ta big Ta unsigned 238.It riscv64 Ta little Ta signed 239.It riscv64sf Ta little Ta signed 240.It sparc64 Ta big Ta signed 241.El 242.Ss Page Size 243.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" 244.It Sy Architecture Ta Sy Page Sizes 245.It amd64 Ta 4K, 2M, 1G 246.It arm Ta 4K 247.It armeb Ta 4K 248.It armv6 Ta 4K, 1M 249.It arm64 Ta 4K, 2M, 1G 250.It i386 Ta 4K, 2M (PAE), 4M 251.It mips Ta 4K 252.It mipsel Ta 4K 253.It mipselhf Ta 4K 254.It mipshf Ta 4K 255.It mipsn32 Ta 4K 256.It mips64 Ta 4K 257.It mips64el Ta 4K 258.It mips64elhf Ta 4K 259.It mips64hf Ta 4K 260.It powerpc Ta 4K 261.It powerpcspe Ta 4K 262.It powerpc64 Ta 4K 263.It riscv64 Ta 4K 264.It riscv64sf Ta 4K 265.It sparc64 Ta 8K 266.El 267.Ss Floating Point 268.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" 269.It Sy Architecture Ta Sy float, double Ta Sy long double 270.It amd64 Ta hard Ta hard, 80 bit 271.It arm Ta soft Ta soft, double precision 272.It armeb Ta soft Ta soft, double precision 273.It armv6 Ta hard(1) Ta hard, double precision 274.It arm64 Ta hard Ta soft, quad precision 275.It i386 Ta hard Ta hard, 80 bit 276.It mips Ta soft Ta identical to double 277.It mipsel Ta soft Ta identical to double 278.It mipselhf Ta hard Ta identical to double 279.It mipshf Ta hard Ta identical to double 280.It mipsn32 Ta soft Ta identical to double 281.It mips64 Ta soft Ta identical to double 282.It mips64el Ta soft Ta identical to double 283.It mips64elhf Ta hard Ta identical to double 284.It mips64hf Ta hard Ta identical to double 285.It powerpc Ta hard Ta hard, double precision 286.It powerpcspe Ta hard Ta hard, double precision 287.It powerpc64 Ta hard Ta hard, double precision 288.It riscv64 Ta hard Ta hard, double precision 289.It riscv64sf Ta soft Ta soft, double precision 290.It sparc64 Ta hard Ta hard, quad precision 291.El 292.Pp 293(1) Prior to 294.Fx 11.0 , 295armv6 used the softfp ABI even though it supported only processors 296with a floating point unit. 297.Ss Predefined Macros 298The compiler provides a number of predefined macros. 299Some of these provide architecture-specific details and are explained below. 300Other macros, including those required by the language standard, are not 301included here. 302.Pp 303The full set of predefined macros can be obtained with this command: 304.Bd -literal -offset indent 305cc -x c -dM -E /dev/null 306.Ed 307.Pp 308Common type size and endianness macros: 309.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning" 310.It Sy Macro Ta Sy Meaning 311.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 312.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 313.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 314.Dv PDP11_ENDIAN 315is not used on 316.Fx . 317.El 318.Pp 319Architecture-specific macros: 320.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" 321.It Sy Architecture Ta Sy Predefined macros 322.It amd64 Ta Dv __amd64__, Dv __x86_64__ 323.It arm Ta Dv __arm__ 324.It armeb Ta Dv __arm__ 325.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 326.It arm64 Ta Dv __aarch64__ 327.It i386 Ta Dv __i386__ 328.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 329.It mipsel Ta Dv __mips__, Dv __mips_o32 330.It mipselhf Ta Dv __mips__, Dv __mips_o32 331.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 332.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 333.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 334.It mips64el Ta Dv __mips__, Dv __mips_n64 335.It mips64elhf Ta Dv __mips__, Dv __mips_n64 336.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 337.It powerpc Ta Dv __powerpc__ 338.It powerpcspe Ta Dv __powerpc__, Dv __SPE__ 339.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ 340.It riscv64 Ta Dv __riscv__, Dv __riscv64 341.It riscv64sf Ta Dv __riscv__, Dv __riscv64 342.It sparc64 Ta Dv __sparc64__ 343.El 344.Sh SEE ALSO 345.Xr src.conf 5 , 346.Xr build 7 347.Sh HISTORY 348An 349.Nm 350manual page appeared in 351.Fx 12 . 352