1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd November 25, 2021 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 12.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g., 72.Dv powerpc 73and AIM variants of 74.Dv powerpc64 , 75the kernel uses a separate address space. 76On other architectures, kernel and a user mode process share a 77single address space. 78The kernel is located at the highest addresses. 79.Pp 80On each architecture, the main user mode thread's stack starts near 81the highest user address and grows down. 82.Pp 83.Fx 84architecture support varies by release. 85This table shows currently supported CPU architectures along with the first 86.Fx 87release to support each architecture. 88.Bl -column -offset indent "Architecture" "Initial Release" 89.It Sy Architecture Ta Sy Initial Release 90.It aarch64 Ta 11.0 91.It amd64 Ta 5.1 92.It armv6 Ta 10.0 93.It armv7 Ta 12.0 94.It i386 Ta 1.0 95.It powerpc Ta 6.0 96.It powerpcspe Ta 12.0 97.It powerpc64 Ta 9.0 98.It powerpc64le Ta 13.0 99.It riscv64 Ta 12.0 100.It riscv64sf Ta 12.0 101.El 102.Pp 103Discontinued architectures are shown in the following table. 104.Bl -column -offset indent "Architecture" "Initial Release" "Final Release" 105.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 106.It alpha Ta 3.2 Ta 6.4 107.It arm Ta 6.0 Ta 12.x 108.It armeb Ta 8.0 Ta 11.4 109.It ia64 Ta 5.0 Ta 10.4 110.It mips Ta 8.0 Ta 13.x 111.It mipsel Ta 9.0 Ta 13.x 112.It mipselhf Ta 12.0 Ta 13.x 113.It mipshf Ta 12.0 Ta 13.x 114.It mipsn32 Ta 9.0 Ta 13.x 115.It mips64 Ta 9.0 Ta 13.x 116.It mips64el Ta 9.0 Ta 13.x 117.It mips64elhf Ta 12.0 Ta 13.x 118.It mips64hf Ta 12.0 Ta 13.x 119.It pc98 Ta 2.2 Ta 11.4 120.It sparc64 Ta 5.0 Ta 12.x 121.El 122.Ss Type sizes 123All 124.Fx 125architectures use some variant of the ELF (see 126.Xr elf 5 ) 127.Sy Application Binary Interface 128(ABI) for the machine processor. 129All supported ABIs can be divided into two groups: 130.Bl -tag -width "Dv ILP32" 131.It Dv ILP32 132.Vt int , 133.Vt long , 134.Vt void * 135types machine representations all have 4-byte size. 136.It Dv LP64 137.Vt int 138type machine representation uses 4 bytes, 139while 140.Vt long 141and 142.Vt void * 143are 8 bytes. 144.El 145.Pp 146Some machines support more than one 147.Fx 148ABI. 149Typically these are 64-bit machines, where the 150.Dq native 151.Dv LP64 152execution environment is accompanied by the 153.Dq legacy 154.Dv ILP32 155environment, which was the historical 32-bit predecessor for 64-bit evolution. 156Examples are: 157.Bl -column -offset indent "powerpc64" "ILP32 counterpart" 158.It Sy LP64 Ta Sy ILP32 counterpart 159.It Dv amd64 Ta Dv i386 160.It Dv powerpc64 Ta Dv powerpc 161.It Dv mips64* Ta Dv mips* 162.It Dv aarch64 Ta Dv armv6/armv7 163.El 164.Pp 165.Dv aarch64 166will support execution of 167.Dv armv6 168or 169.Dv armv7 170binaries if the CPU implements 171.Dv AArch32 172execution state, however 173.Dv armv5 174binaries aren't supported. 175.Pp 176On all supported architectures: 177.Bl -column -offset -indent "long long" "Size" 178.It Sy Type Ta Sy Size 179.It short Ta 2 180.It int Ta 4 181.It long Ta sizeof(void*) 182.It long long Ta 8 183.It float Ta 4 184.It double Ta 8 185.El 186.Pp 187Integers are represented in two's complement. 188Alignment of integer and pointer types is natural, that is, 189the address of the variable must be congruent to zero modulo the type size. 190Most ILP32 ABIs, except 191.Dv arm , 192require only 4-byte alignment for 64-bit integers. 193.Pp 194Machine-dependent type sizes: 195.Bl -column -offset indent "Architecture" "void *" "long double" "time_t" 196.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 197.It aarch64 Ta 8 Ta 16 Ta 8 198.It amd64 Ta 8 Ta 16 Ta 8 199.It armv6 Ta 4 Ta 8 Ta 8 200.It armv7 Ta 4 Ta 8 Ta 8 201.It i386 Ta 4 Ta 12 Ta 4 202.It mips Ta 4 Ta 8 Ta 8 203.It mipsel Ta 4 Ta 8 Ta 8 204.It mipselhf Ta 4 Ta 8 Ta 8 205.It mipshf Ta 4 Ta 8 Ta 8 206.It mipsn32 Ta 4 Ta 8 Ta 8 207.It mips64 Ta 8 Ta 8 Ta 8 208.It mips64el Ta 8 Ta 8 Ta 8 209.It mips64elhf Ta 8 Ta 8 Ta 8 210.It mips64hf Ta 8 Ta 8 Ta 8 211.It powerpc Ta 4 Ta 8 Ta 8 212.It powerpcspe Ta 4 Ta 8 Ta 8 213.It powerpc64 Ta 8 Ta 8 Ta 8 214.It powerpc64le Ta 8 Ta 8 Ta 8 215.It riscv64 Ta 8 Ta 16 Ta 8 216.It riscv64sf Ta 8 Ta 16 Ta 8 217.El 218.Pp 219.Sy time_t 220is 8 bytes on all supported architectures except i386. 221.Ss Endianness and Char Signedness 222.Bl -column -offset indent "Architecture" "Endianness" "char Signedness" 223.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 224.It aarch64 Ta little Ta unsigned 225.It amd64 Ta little Ta signed 226.It armv6 Ta little Ta unsigned 227.It armv7 Ta little Ta unsigned 228.It i386 Ta little Ta signed 229.It mips Ta big Ta signed 230.It mipsel Ta little Ta signed 231.It mipselhf Ta little Ta signed 232.It mipshf Ta big Ta signed 233.It mipsn32 Ta big Ta signed 234.It mips64 Ta big Ta signed 235.It mips64el Ta little Ta signed 236.It mips64elhf Ta little Ta signed 237.It mips64hf Ta big Ta signed 238.It powerpc Ta big Ta unsigned 239.It powerpcspe Ta big Ta unsigned 240.It powerpc64 Ta big Ta unsigned 241.It powerpc64le Ta little Ta unsigned 242.It riscv64 Ta little Ta signed 243.It riscv64sf Ta little Ta signed 244.El 245.Ss Page Size 246.Bl -column -offset indent "Architecture" "Page Sizes" 247.It Sy Architecture Ta Sy Page Sizes 248.It aarch64 Ta 4K, 2M, 1G 249.It amd64 Ta 4K, 2M, 1G 250.It armv6 Ta 4K, 1M 251.It armv7 Ta 4K, 1M 252.It i386 Ta 4K, 2M (PAE), 4M 253.It mips Ta 4K 254.It mipsel Ta 4K 255.It mipselhf Ta 4K 256.It mipshf Ta 4K 257.It mipsn32 Ta 4K 258.It mips64 Ta 4K 259.It mips64el Ta 4K 260.It mips64elhf Ta 4K 261.It mips64hf Ta 4K 262.It powerpc Ta 4K 263.It powerpcspe Ta 4K 264.It powerpc64 Ta 4K 265.It powerpc64le Ta 4K 266.It riscv64 Ta 4K, 2M, 1G 267.It riscv64sf Ta 4K, 2M, 1G 268.El 269.Ss Floating Point 270.Bl -column -offset indent "Architecture" "float, double" "long double" 271.It Sy Architecture Ta Sy float, double Ta Sy long double 272.It aarch64 Ta hard Ta soft, quad precision 273.It amd64 Ta hard Ta hard, 80 bit 274.It armv6 Ta hard Ta hard, double precision 275.It armv7 Ta hard Ta hard, double precision 276.It i386 Ta hard Ta hard, 80 bit 277.It mips Ta soft Ta identical to double 278.It mipsel Ta soft Ta identical to double 279.It mipselhf Ta hard Ta identical to double 280.It mipshf Ta hard Ta identical to double 281.It mipsn32 Ta soft Ta identical to double 282.It mips64 Ta soft Ta identical to double 283.It mips64el Ta soft Ta identical to double 284.It mips64elhf Ta hard Ta identical to double 285.It mips64hf Ta hard Ta identical to double 286.It powerpc Ta hard Ta hard, double precision 287.It powerpcspe Ta hard Ta hard, double precision 288.It powerpc64 Ta hard Ta hard, double precision 289.It powerpc64le Ta hard Ta hard, double precision 290.It riscv64 Ta hard Ta hard, quad precision 291.It riscv64sf Ta soft Ta soft, quad precision 292.El 293.Ss Default Tool Chain 294.Fx 295uses 296.Xr clang 1 297as the default compiler on all supported CPU architectures, 298LLVM's 299.Xr ld.lld 1 300as the default linker, and 301ELF Tool Chain binary utilities such as 302.Xr objcopy 1 303and 304.Xr readelf 1 . 305.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE 306.Dv MACHINE_CPUARCH 307should be preferred in Makefiles when the generic 308architecture is being tested. 309.Dv MACHINE_ARCH 310should be preferred when there is something specific to a particular type of 311architecture where there is a choice of many, or could be a choice of many. 312Use 313.Dv MACHINE 314when referring to the kernel, interfaces dependent on a specific type of kernel 315or similar things like boot sequences. 316.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH" 317.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH 318.It arm64 Ta aarch64 Ta aarch64 319.It amd64 Ta amd64 Ta amd64 320.It arm Ta arm Ta armv6, armv7 321.It i386 Ta i386 Ta i386 322.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32 323.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le 324.It riscv Ta riscv Ta riscv64, riscv64sf 325.El 326.Ss Predefined Macros 327The compiler provides a number of predefined macros. 328Some of these provide architecture-specific details and are explained below. 329Other macros, including those required by the language standard, are not 330included here. 331.Pp 332The full set of predefined macros can be obtained with this command: 333.Bd -literal -offset indent 334cc -x c -dM -E /dev/null 335.Ed 336.Pp 337Common type size and endianness macros: 338.Bl -column -offset indent "BYTE_ORDER" "Meaning" 339.It Sy Macro Ta Sy Meaning 340.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 341.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 342.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 343.Dv PDP11_ENDIAN 344is not used on 345.Fx . 346.El 347.Pp 348Architecture-specific macros: 349.Bl -column -offset indent "Architecture" "Predefined macros" 350.It Sy Architecture Ta Sy Predefined macros 351.It aarch64 Ta Dv __aarch64__ 352.It amd64 Ta Dv __amd64__ , Dv __x86_64__ 353.It armv6 Ta Dv __arm__ , Dv __ARM_ARCH >= 6 354.It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7 355.It i386 Ta Dv __i386__ 356.It mips Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32 357.It mipsel Ta Dv __mips__ , Dv __mips_o32 358.It mipselhf Ta Dv __mips__ , Dv __mips_o32 359.It mipshf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32 360.It mipsn32 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n32 361.It mips64 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64 362.It mips64el Ta Dv __mips__ , Dv __mips_n64 363.It mips64elhf Ta Dv __mips__ , Dv __mips_n64 364.It mips64hf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64 365.It powerpc Ta Dv __powerpc__ 366.It powerpcspe Ta Dv __powerpc__ , Dv __SPE__ 367.It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__ 368.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__ 369.It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64 370.It riscv64sf Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __riscv_float_abi_soft 371.El 372.Pp 373Compilers may define additional variants of architecture-specific macros. 374The macros above are preferred for use in 375.Fx . 376.Ss Important Xr make 1 variables 377Most of the externally settable variables are defined in the 378.Xr build 7 379man page. 380These variables are not otherwise documented and are used extensively 381in the build system. 382.Bl -tag -width "MACHINE_CPUARCH" 383.It Dv MACHINE 384Represents the hardware platform. 385This is the same as the native platform's 386.Xr uname 1 387.Fl m 388output. 389It defines both the userland / kernel interface, as well as the 390bootloader / kernel interface. 391It should only be used in these contexts. 392Each CPU architecture may have multiple hardware platforms it supports 393where 394.Dv MACHINE 395differs among them. 396It is used to collect together all the files from 397.Xr config 8 398to build the kernel. 399It is often the same as 400.Dv MACHINE_ARCH 401just as one CPU architecture can be implemented by many different 402hardware platforms, one hardware platform may support multiple CPU 403architecture family members, though with different binaries. 404For example, 405.Dv MACHINE 406of i386 supported the IBM-AT hardware platform while the 407.Dv MACHINE 408of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 409hardware platforms. 410Both of these hardware platforms supported only the 411.Dv MACHINE_ARCH 412of i386 where they shared a common ABI, except for certain kernel / 413userland interfaces relating to underlying hardware platform 414differences in bus architecture, device enumeration and boot interface. 415Generally, 416.Dv MACHINE 417should only be used in src/sys and src/stand or in system imagers or 418installers. 419.It Dv MACHINE_ARCH 420Represents the CPU processor architecture. 421This is the same as the native platforms 422.Xr uname 1 423.Fl p 424output. 425It defines the CPU instruction family supported. 426It may also encode a variation in the byte ordering of multi-byte 427integers (endian). 428It may also encode a variation in the size of the integer or pointer. 429It may also encode a ISA revision. 430It may also encode hard versus soft floating point ABI and usage. 431It may also encode a variant ABI when the other factors do not 432uniquely define the ABI (e.g., MIPS' n32 ABI). 433It, along with 434.Dv MACHINE , 435defines the ABI used by the system. 436For example, the MIPS CPU processor family supports 9 different 437combinations encoding pointer size, endian and hard versus soft float (for 4388 combinations) as well as N32 (which only ever had one variation of 439all these). 440Generally, the plain CPU name specifies the most common (or at least 441first) variant of the CPU. 442This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7' 443imply little endian. 444If we ever were to support the so-called x32 ABI (using 32-bit 445pointers on the amd64 architecture), it would most likely be encoded 446as amd64-x32. 447It is unfortunate that amd64 specifies the 64-bit evolution of the x86 448platform (it matches the 'first rule') as everybody else uses x86_64. 449There is no standard name for the processor: each OS selects its own 450conventions. 451.It Dv MACHINE_CPUARCH 452Represents the source location for a given 453.Dv MACHINE_ARCH . 454It is generally the common prefix for all the MACHINE_ARCH that 455share the same implementation, though 'riscv' breaks this rule. 456For example, 457.Dv MACHINE_CPUARCH 458is defined to be mips for all the flavors of mips that we support 459since we support them all with a shared set of sources. 460While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 461for them. 462The 463.Fx 464source base supports amd64 and i386 with two 465distinct source bases living in subdirectories named amd64 and i386 466(though behind the scenes there's some sharing that fits into this 467framework). 468.It Dv CPUTYPE 469Sets the flavor of 470.Dv MACHINE_ARCH 471to build. 472It is used to optimize the build for a specific CPU / core that the 473binaries run on. 474Generally, this does not change the ABI, though it can be a fine line 475between optimization for specific cases. 476.It Dv TARGET 477Used to set 478.Dv MACHINE 479in the top level Makefile for cross building. 480Unused outside of that scope. 481It is not passed down to the rest of the build. 482Makefiles outside of the top level should not use it at all (though 483some have their own private copy for hysterical raisons). 484.It Dv TARGET_ARCH 485Used to set 486.Dv MACHINE_ARCH 487by the top level Makefile for cross building. 488Like 489.Dv TARGET , 490it is unused outside of that scope. 491.El 492.Sh SEE ALSO 493.Xr src.conf 5 , 494.Xr build 7 495.Sh HISTORY 496An 497.Nm 498manual page appeared in 499.Fx 11.1 . 500