1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd October 9, 2019 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 10.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g., 72.Dv sparc64 , 73.Dv powerpc 74and AIM variants of 75.Dv powerpc64 , 76the kernel uses a separate address space. 77On other architectures, kernel and a user mode process share a 78single address space. 79The kernel is located at the highest addresses. 80.Pp 81On each architecture, the main user mode thread's stack starts near 82the highest user address and grows down. 83.Pp 84.Fx 85architecture support varies by release. 86This table shows the first 87.Fx 88release to support each architecture, and, for discontinued 89architectures, the final release. 90.Pp 91.Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release" 92.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 93.It aarch64 Ta 11.0 94.It alpha Ta 3.2 Ta 6.4 95.It amd64 Ta 5.1 96.It arm Ta 6.0 Ta 12.x 97.It armeb Ta 8.0 Ta 11.x 98.It armv6 Ta 10.0 99.It armv7 Ta 12.0 100.It ia64 Ta 5.0 Ta 10.4 101.It i386 Ta 1.0 102.It mips Ta 8.0 103.It mipsel Ta 9.0 104.It mipselhf Ta 12.0 105.It mipshf Ta 12.0 106.It mipsn32 Ta 9.0 107.It mips64 Ta 9.0 108.It mips64el Ta 9.0 109.It mips64elhf Ta 12.0 110.It mips64hf Ta 12.0 111.It pc98 Ta 2.2 Ta 11.x 112.It powerpc Ta 6.0 113.It powerpcspe Ta 12.0 114.It powerpc64 Ta 6.0 115.It riscv64 Ta 12.0 116.It riscv64sf Ta 12.0 117.It sparc64 Ta 5.0 118.El 119.Ss Type sizes 120All 121.Fx 122architectures use some variant of the ELF (see 123.Xr elf 5 ) 124.Sy Application Binary Interface 125(ABI) for the machine processor. 126All supported ABIs can be divided into two groups: 127.Bl -tag -width "Dv ILP32" 128.It Dv ILP32 129.Vt int , 130.Vt long , 131.Vt void * 132types machine representations all have 4-byte size. 133.It Dv LP64 134.Vt int 135type machine representation uses 4 bytes, 136while 137.Vt long 138and 139.Vt void * 140are 8 bytes. 141.El 142Compilers define the 143.Dv _LP64 144symbol when compiling for an 145.Dv LP64 146ABI. 147.Pp 148Some machines support more that one 149.Fx 150ABI. 151Typically these are 64-bit machines, where the 152.Dq native 153.Dv LP64 154execution environment is accompanied by the 155.Dq legacy 156.Dv ILP32 157environment, which was historical 32-bit predecessor for 64-bit evolution. 158Examples are: 159.Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart" 160.It Sy LP64 Ta Sy ILP32 counterpart 161.It Dv amd64 Ta Dv i386 162.It Dv powerpc64 Ta Dv powerpc 163.It Dv mips64* Ta Dv mips* 164.El 165.Dv aarch64 166currently does not support execution of 167.Dv armv6 168or 169.Dv armv7 170binaries, even if the CPU implements 171.Dv AArch32 172execution state. 173.Pp 174On all supported architectures: 175.Bl -column -offset -indent "long long" "Size" 176.It Sy Type Ta Sy Size 177.It short Ta 2 178.It int Ta 4 179.It long Ta sizeof(void*) 180.It long long Ta 8 181.It float Ta 4 182.It double Ta 8 183.El 184Integers are represented in two's complement. 185Alignment of integer and pointer types is natural, that is, 186the address of the variable must be congruent to zero modulo the type size. 187Most ILP32 ABIs, except 188.Dv arm , 189require only 4-byte alignment for 64-bit integers. 190.Pp 191Machine-dependent type sizes: 192.Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t" 193.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 194.It aarch64 Ta 8 Ta 16 Ta 8 195.It amd64 Ta 8 Ta 16 Ta 8 196.It arm Ta 4 Ta 8 Ta 8 197.It armv6 Ta 4 Ta 8 Ta 8 198.It i386 Ta 4 Ta 12 Ta 4 199.It mips Ta 4 Ta 8 Ta 8 200.It mipsel Ta 4 Ta 8 Ta 8 201.It mipselhf Ta 4 Ta 8 Ta 8 202.It mipshf Ta 4 Ta 8 Ta 8 203.It mipsn32 Ta 4 Ta 8 Ta 8 204.It mips64 Ta 8 Ta 8 Ta 8 205.It mips64el Ta 8 Ta 8 Ta 8 206.It mips64elhf Ta 8 Ta 8 Ta 8 207.It mips64hf Ta 8 Ta 8 Ta 8 208.It powerpc Ta 4 Ta 8 Ta 8 209.It powerpcspe Ta 4 Ta 8 Ta 8 210.It powerpc64 Ta 8 Ta 8 Ta 8 211.It riscv64 Ta 8 Ta 16 Ta 8 212.It riscv64sf Ta 8 Ta 16 Ta 8 213.It sparc64 Ta 8 Ta 16 Ta 8 214.El 215.Pp 216.Sy time_t 217is 8 bytes on all supported architectures except i386. 218.Ss Endianness and Char Signedness 219.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" 220.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 221.It aarch64 Ta little Ta unsigned 222.It amd64 Ta little Ta signed 223.It arm Ta little Ta unsigned 224.It armv6 Ta little Ta unsigned 225.It armv7 Ta little Ta unsigned 226.It i386 Ta little Ta signed 227.It mips Ta big Ta signed 228.It mipsel Ta little Ta signed 229.It mipselhf Ta little Ta signed 230.It mipshf Ta big Ta signed 231.It mipsn32 Ta big Ta signed 232.It mips64 Ta big Ta signed 233.It mips64el Ta little Ta signed 234.It mips64elhf Ta little Ta signed 235.It mips64hf Ta big Ta signed 236.It powerpc Ta big Ta unsigned 237.It powerpcspe Ta big Ta unsigned 238.It powerpc64 Ta big Ta unsigned 239.It riscv64 Ta little Ta signed 240.It riscv64sf Ta little Ta signed 241.It sparc64 Ta big Ta signed 242.El 243.Ss Page Size 244.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" 245.It Sy Architecture Ta Sy Page Sizes 246.It aarch64 Ta 4K, 2M, 1G 247.It amd64 Ta 4K, 2M, 1G 248.It arm Ta 4K 249.It armv6 Ta 4K, 1M 250.It armv7 Ta 4K, 1M 251.It i386 Ta 4K, 2M (PAE), 4M 252.It mips Ta 4K 253.It mipsel Ta 4K 254.It mipselhf Ta 4K 255.It mipshf Ta 4K 256.It mipsn32 Ta 4K 257.It mips64 Ta 4K 258.It mips64el Ta 4K 259.It mips64elhf Ta 4K 260.It mips64hf Ta 4K 261.It powerpc Ta 4K 262.It powerpcspe Ta 4K 263.It powerpc64 Ta 4K 264.It riscv64 Ta 4K 265.It riscv64sf Ta 4K 266.It sparc64 Ta 8K 267.El 268.Ss Floating Point 269.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" 270.It Sy Architecture Ta Sy float, double Ta Sy long double 271.It aarch64 Ta hard Ta soft, quad precision 272.It amd64 Ta hard Ta hard, 80 bit 273.It arm Ta soft Ta soft, double precision 274.It armv6 Ta hard(1) Ta hard, double precision 275.It armv7 Ta hard(1) Ta hard, double precision 276.It i386 Ta hard Ta hard, 80 bit 277.It mips Ta soft Ta identical to double 278.It mipsel Ta soft Ta identical to double 279.It mipselhf Ta hard Ta identical to double 280.It mipshf Ta hard Ta identical to double 281.It mipsn32 Ta soft Ta identical to double 282.It mips64 Ta soft Ta identical to double 283.It mips64el Ta soft Ta identical to double 284.It mips64elhf Ta hard Ta identical to double 285.It mips64hf Ta hard Ta identical to double 286.It powerpc Ta hard Ta hard, double precision 287.It powerpcspe Ta hard Ta hard, double precision 288.It powerpc64 Ta hard Ta hard, double precision 289.It riscv64 Ta hard Ta hard, double precision 290.It riscv64sf Ta soft Ta soft, double precision 291.It sparc64 Ta hard Ta hard, quad precision 292.El 293.Pp 294(1) Prior to 295.Fx 11.0 , 296armv6 used the softfp ABI even though it supported only processors 297with a floating point unit. 298.Ss Default Tool Chain 299.Fx uses a variety of tool chain components for the supported CPU 300architectures: 301.Xr clang 1 302and 303.Xr ld.lld 1 304provided by the base system, 305GNU 306.Xr gcc 1 307and Binutils 308.Xr ld 1 , 309or an external toolchain compiler and linker provided by a port or package. 310This table shows the default tool chain for each architecture. 311.Bl -column -offset indent "Sy Architecture" "Sy Compiler" "Sy Linker" 312.It Sy Architecture Ta Sy Compiler Ta Sy Linker 313.It aarch64 Ta Clang Ta lld 314.It amd64 Ta Clang Ta lld 315.It arm Ta Clang Ta GNU ld 2.17.50 316.It armv6 Ta Clang Ta GNU ld 2.17.50 317.It armv7 Ta Clang Ta lld 318.It i386 Ta Clang Ta lld 319.It mips Ta GCC 4.2.1 Ta GNU ld 2.17.50 320.It mipsel Ta GCC 4.2.1 Ta GNU ld 2.17.50 321.It mipselhf Ta GCC 4.2.1 Ta GNU ld 2.17.50 322.It mipshf Ta GCC 4.2.1 Ta GNU ld 2.17.50 323.It mipsn32 Ta GCC 4.2.1 Ta GNU ld 2.17.50 324.It mips64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 325.It mips64el Ta GCC 4.2.1 Ta GNU ld 2.17.50 326.It mips64elhf Ta GCC 4.2.1 Ta GNU ld 2.17.50 327.It mips64hf Ta GCC 4.2.1 Ta GNU ld 2.17.50 328.It powerpc Ta GCC 4.2.1 Ta GNU ld 2.17.50 329.It powerpcspe Ta GCC 4.2.1 Ta GNU ld 2.17.50 330.It powerpc64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 331.It riscv64 Ta GCC(1) Ta GNU ld(1) 332.It riscv64sf Ta GCC(1) Ta GNU ld(1) 333.It sparc64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 334.El 335.Pp 336(1) External toolchain provided by ports/packages. 337.Pp 338Note that GCC 4.2.1 is deprecated, and scheduled for removal on 2020-03-31. 339Any CPU architectures not migrated by then 340(to either base system Clang or external toolchain) 341may be removed from the tree after that date. 342Unless the make variable 343.Dv MAKE_OBSOLETE_GCC 344is defined, make universe will not build mips, powerpc, nor sparc64 345architectures unless the xtoolchain binaries have been installed for 346the architecture. 347.Ss Predefined Macros 348The compiler provides a number of predefined macros. 349Some of these provide architecture-specific details and are explained below. 350Other macros, including those required by the language standard, are not 351included here. 352.Pp 353The full set of predefined macros can be obtained with this command: 354.Bd -literal -offset indent 355cc -x c -dM -E /dev/null 356.Ed 357.Pp 358Common type size and endianness macros: 359.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning" 360.It Sy Macro Ta Sy Meaning 361.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 362.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 363.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 364.Dv PDP11_ENDIAN 365is not used on 366.Fx . 367.El 368.Pp 369Architecture-specific macros: 370.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" 371.It Sy Architecture Ta Sy Predefined macros 372.It aarch64 Ta Dv __aarch64__ 373.It amd64 Ta Dv __amd64__, Dv __x86_64__ 374.It arm Ta Dv __arm__ 375.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 376.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7 377.It i386 Ta Dv __i386__ 378.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 379.It mipsel Ta Dv __mips__, Dv __mips_o32 380.It mipselhf Ta Dv __mips__, Dv __mips_o32 381.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 382.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 383.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 384.It mips64el Ta Dv __mips__, Dv __mips_n64 385.It mips64elhf Ta Dv __mips__, Dv __mips_n64 386.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 387.It powerpc Ta Dv __powerpc__ 388.It powerpcspe Ta Dv __powerpc__, Dv __SPE__ 389.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ 390.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 391.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 392.It sparc64 Ta Dv __sparc64__ 393.El 394.Pp 395Compilers may define additional variants of architecture-specific macros. 396The macros above are preferred for use in 397.Fx . 398.Ss Important Xr make 1 variables 399Most of the externally settable variables are defined in the 400.Xr build 7 401man page. 402These variables are not otherwise documented and are used extensively 403in the build system. 404.Bl -column -offset indent "Sy Variable" "Sy Meaning and usage" 405.It Dv MACHINE Represent the hardware platform. 406This is the same as the native platform's 407.Xr uname 1 408.Fl m 409output. 410It defines both the userland / kernel interface, as well as the 411bootloader / kernel interface. 412It should only be used in these contexts. 413Each CPU architecture may have multiple hardware platforms it supports 414where 415.Dv MACHINE 416differs among them. 417It is used to collect together all the files from 418.Xr config 8 419to build the kernel. 420It is often the same as 421.Dv MACHINE_ARCH 422just as one CPU architecture can be implemented by many different 423hardware platforms, one hardware platform may support multiple CPU 424architecture family members, though with different binaries. 425For example, 426.Dv MACHINE 427of i386 supported the IBM-AT hardware platform while the 428.Dv MACHINE 429of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 430hardware platforms. 431Both of these hardware platforms supported only the 432.Dv MACHINE_ARCH 433of i386 where they shared a common ABI, except for certain kernel / 434userland interfaces relating to underlying hardware platform 435differences in bus architecture, device enumeration and boot interface. 436Generally, 437.Dv MACHINE 438should only be used in src/sys and src/stand or in system imagers or 439installers. 440.It Dv MACHINE_ARCH Represents the CPU processor architecture. 441This is the same as the native platforms 442.Xr uname 1 443.Fl p 444output. 445It defines the CPU instruction family supported. 446It may also encode a variation in the byte ordering of multi-byte 447integers (endian). 448It may also encode a variation in the size of the integer or pointer. 449It may also encode a ISA revision. 450It may also encode hard versus soft floating point ABI and usage. 451It may also encode a variant ABI when the other factors do not 452uniquely define the ABI (e.g., MIPS' n32 ABI). 453It, along with 454.Dv MACHINE , 455defines the ABI used by the system. 456For example, the MIPS CPU processor family supports 9 different 457combinations encoding pointer size, endian and hard versus soft float (for 4588 combinations) as well as N32 (which only ever had one variation of 459all these). 460Generally, the plain CPU name specifies the most common (or at least 461first) variant of the CPU. 462This is why mips and mips64 imply 'big endian' while 'arm' and 'armv7' 463imply little endian. 464If we ever were to support the so-called x32 ABI (using 32-bit 465pointers on the amd64 architecture), it would most likely be encoded 466as amd64-x32. 467It is unfortunate that amd64 specifies the 64-bit evolution of the x86 468platform (it matches the 'first rule') as everybody else uses x86_64. 469There is no standard name for the processor: each OS selects its own 470conventions. 471.It Dv MACHINE_CPUARCH Represents the source location for a given 472.Dv MACHINE_ARCH . 473For example, 474.Dv MACHINE_CPUARCH 475is defined to be mips for all the flavors of mips that we support 476since we support them all with a shared set of sources. 477While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 478for them. 479The FreeBSD source base supports amd64 and i386 with two 480distinct source bases living in subdirectories named amd64 and i386 481(though behind the scenes there's some sharing that fits into this 482framework). 483.It Dv CPUTYPE Sets the flavor of 484.Dv MACHINE_ARCH 485to build. 486It is used to optimize the build for a specific CPU / core that the 487binaries run on. 488Generally, this does not change the ABI, though it can be a fine line 489between optimization for specific cases. 490.It Dv TARGET Used to set 491.Dv MACHINE 492in the top level Makefile for cross building. 493Unused outside of that scope. 494It is not passed down to the rest of the build. 495Makefiles outside of the top level should not use it at all (though 496some have their own private copy for hysterical raisons). 497.It Dv TARGET_ARCH Used to set 498.Dv MACHINE_ARCH 499by the top level Makefile for cross building. 500Like 501.Dv TARGET , it is unused outside of that scope. 502.El 503.Sh SEE ALSO 504.Xr src.conf 5 , 505.Xr build 7 506.Sh HISTORY 507An 508.Nm 509manual page appeared in 510.Fx 11.1 . 511