xref: /freebsd/share/man/man7/arch.7 (revision 4d3fc8b0570b29fb0d6ee9525f104d52176ff0d4)
1.\" Copyright (c) 2016-2017 The FreeBSD Foundation.
2.\"
3.\" This documentation was created by Ed Maste under sponsorship of
4.\" The FreeBSD Foundation.
5.\"
6.\" Redistribution and use in source and binary forms, with or without
7.\" modification, are permitted provided that the following conditions
8.\" are met:
9.\" 1. Redistributions of source code must retain the above copyright
10.\"    notice, this list of conditions and the following disclaimer.
11.\" 2. Redistributions in binary form must reproduce the above copyright
12.\"    notice, this list of conditions and the following disclaimer in the
13.\"    documentation and/or other materials provided with the distribution.
14.\"
15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND
16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25.\" SUCH DAMAGE.
26.\"
27.\" $FreeBSD$
28.\"
29.Dd March 8, 2023
30.Dt ARCH 7
31.Os
32.Sh NAME
33.Nm arch
34.Nd Architecture-specific details
35.Sh DESCRIPTION
36Differences between CPU architectures and platforms supported by
37.Fx .
38.Ss Introduction
39This document is a quick reference of key ABI details of
40.Fx
41architecture ports.
42For full details consult the processor-specific ABI supplement
43documentation.
44.Pp
45If not explicitly mentioned, sizes are in bytes.
46The architecture details in this document apply to
47.Fx 12.0
48and later, unless otherwise noted.
49.Pp
50.Fx
51uses a flat address space.
52Variables of types
53.Vt unsigned long ,
54.Vt uintptr_t ,
55and
56.Vt size_t
57and pointers all have the same representation.
58.Pp
59In order to maximize compatibility with future pointer integrity mechanisms,
60manipulations of pointers as integers should be performed via
61.Vt uintptr_t
62or
63.Vt intptr_t
64and no other types.
65In particular,
66.Vt long
67and
68.Vt ptrdiff_t
69should be avoided.
70.Pp
71On some architectures, e.g.,
72.Dv powerpc
73and AIM variants of
74.Dv powerpc64 ,
75the kernel uses a separate address space.
76On other architectures, kernel and a user mode process share a
77single address space.
78The kernel is located at the highest addresses.
79.Pp
80On each architecture, the main user mode thread's stack starts near
81the highest user address and grows down.
82.Pp
83.Fx
84architecture support varies by release.
85This table shows currently supported CPU architectures along with the first
86.Fx
87release to support each architecture.
88.Bl -column -offset indent "Architecture" "Initial Release"
89.It Sy Architecture Ta Sy Initial Release
90.It aarch64     Ta 11.0
91.It amd64       Ta 5.1
92.It armv6       Ta 10.0
93.It armv7       Ta 12.0
94.It i386        Ta 1.0
95.It powerpc     Ta 6.0
96.It powerpcspe  Ta 12.0
97.It powerpc64   Ta 9.0
98.It powerpc64le Ta 13.0
99.It riscv64     Ta 12.0
100.It riscv64sf   Ta 12.0
101.El
102.Pp
103Discontinued architectures are shown in the following table.
104.Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
105.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
106.It alpha       Ta 3.2   Ta 6.4
107.It arm         Ta 6.0   Ta 12.x
108.It armeb       Ta 8.0   Ta 11.4
109.It ia64        Ta 5.0   Ta 10.4
110.It mips        Ta 8.0   Ta 13.x
111.It mipsel      Ta 9.0   Ta 13.x
112.It mipselhf    Ta 12.0  Ta 13.x
113.It mipshf      Ta 12.0  Ta 13.x
114.It mipsn32     Ta 9.0   Ta 13.x
115.It mips64      Ta 9.0   Ta 13.x
116.It mips64el    Ta 9.0   Ta 13.x
117.It mips64elhf  Ta 12.0  Ta 13.x
118.It mips64hf    Ta 12.0  Ta 13.x
119.It pc98        Ta 2.2   Ta 11.4
120.It sparc64     Ta 5.0   Ta 12.x
121.El
122.Ss Type sizes
123All
124.Fx
125architectures use some variant of the ELF (see
126.Xr elf 5 )
127.Sy Application Binary Interface
128(ABI) for the machine processor.
129All supported ABIs can be divided into two groups:
130.Bl -tag -width "Dv ILP32"
131.It Dv ILP32
132.Vt int ,
133.Vt long ,
134.Vt void *
135types machine representations all have 4-byte size.
136.It Dv LP64
137.Vt int
138type machine representation uses 4 bytes,
139while
140.Vt long
141and
142.Vt void *
143are 8 bytes.
144.El
145.Pp
146Some machines support more than one
147.Fx
148ABI.
149Typically these are 64-bit machines, where the
150.Dq native
151.Dv LP64
152execution environment is accompanied by the
153.Dq legacy
154.Dv ILP32
155environment, which was the historical 32-bit predecessor for 64-bit evolution.
156Examples are:
157.Bl -column -offset indent "powerpc64" "ILP32 counterpart"
158.It Sy LP64        Ta Sy ILP32 counterpart
159.It Dv amd64       Ta Dv i386
160.It Dv powerpc64   Ta Dv powerpc
161.It Dv aarch64     Ta Dv armv6/armv7
162.El
163.Pp
164.Dv aarch64
165will support execution of
166.Dv armv6
167or
168.Dv armv7
169binaries if the CPU implements
170.Dv AArch32
171execution state, however older
172.Dv armv4
173and
174.Dv armv5
175binaries aren't supported.
176.Pp
177On all supported architectures:
178.Bl -column -offset -indent "long long" "Size"
179.It Sy Type Ta Sy Size
180.It short Ta 2
181.It int Ta 4
182.It long Ta sizeof(void*)
183.It long long Ta 8
184.It float Ta 4
185.It double Ta 8
186.El
187.Pp
188Integers are represented in two's complement.
189Alignment of integer and pointer types is natural, that is,
190the address of the variable must be congruent to zero modulo the type size.
191Most ILP32 ABIs, except
192.Dv arm ,
193require only 4-byte alignment for 64-bit integers.
194.Pp
195Machine-dependent type sizes:
196.Bl -column -offset indent "Architecture" "void *" "long double" "time_t"
197.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
198.It aarch64     Ta 8 Ta 16 Ta 8
199.It amd64       Ta 8 Ta 16 Ta 8
200.It armv6       Ta 4 Ta  8 Ta 8
201.It armv7       Ta 4 Ta  8 Ta 8
202.It i386        Ta 4 Ta 12 Ta 4
203.It powerpc     Ta 4 Ta  8 Ta 8
204.It powerpcspe  Ta 4 Ta  8 Ta 8
205.It powerpc64   Ta 8 Ta  8 Ta 8
206.It powerpc64le Ta 8 Ta  8 Ta 8
207.It riscv64     Ta 8 Ta 16 Ta 8
208.It riscv64sf   Ta 8 Ta 16 Ta 8
209.El
210.Pp
211.Sy time_t
212is 8 bytes on all supported architectures except i386.
213.Ss Endianness and Char Signedness
214.Bl -column -offset indent "Architecture" "Endianness" "char Signedness"
215.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
216.It aarch64     Ta little Ta unsigned
217.It amd64       Ta little Ta   signed
218.It armv6       Ta little Ta unsigned
219.It armv7       Ta little Ta unsigned
220.It i386        Ta little Ta   signed
221.It powerpc     Ta big    Ta unsigned
222.It powerpcspe  Ta big    Ta unsigned
223.It powerpc64   Ta big    Ta unsigned
224.It powerpc64le Ta little Ta unsigned
225.It riscv64     Ta little Ta   signed
226.It riscv64sf   Ta little Ta   signed
227.El
228.Ss Page Size
229.Bl -column -offset indent "Architecture" "Page Sizes"
230.It Sy Architecture Ta Sy Page Sizes
231.It aarch64     Ta 4K, 2M, 1G
232.It amd64       Ta 4K, 2M, 1G
233.It armv6       Ta 4K, 1M
234.It armv7       Ta 4K, 1M
235.It i386        Ta 4K, 2M (PAE), 4M
236.It powerpc     Ta 4K
237.It powerpcspe  Ta 4K
238.It powerpc64   Ta 4K
239.It powerpc64le Ta 4K
240.It riscv64     Ta 4K, 2M, 1G
241.It riscv64sf   Ta 4K, 2M, 1G
242.El
243.Ss Floating Point
244.Bl -column -offset indent "Architecture" "float, double" "long double"
245.It Sy Architecture Ta Sy float, double Ta Sy long double
246.It aarch64     Ta hard Ta soft, quad precision
247.It amd64       Ta hard Ta hard, 80 bit
248.It armv6       Ta hard Ta hard, double precision
249.It armv7       Ta hard Ta hard, double precision
250.It i386        Ta hard Ta hard, 80 bit
251.It powerpc     Ta hard Ta hard, double precision
252.It powerpcspe  Ta hard Ta hard, double precision
253.It powerpc64   Ta hard Ta hard, double precision
254.It powerpc64le Ta hard Ta hard, double precision
255.It riscv64     Ta hard Ta hard, quad precision
256.It riscv64sf   Ta soft Ta soft, quad precision
257.El
258.Ss Default Tool Chain
259.Fx
260uses
261.Xr clang 1
262as the default compiler on all supported CPU architectures,
263LLVM's
264.Xr ld.lld 1
265as the default linker, and
266ELF Tool Chain binary utilities such as
267.Xr objcopy 1
268and
269.Xr readelf 1 .
270.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE
271.Dv MACHINE_CPUARCH
272should be preferred in Makefiles when the generic
273architecture is being tested.
274.Dv MACHINE_ARCH
275should be preferred when there is something specific to a particular type of
276architecture where there is a choice of many, or could be a choice of many.
277Use
278.Dv MACHINE
279when referring to the kernel, interfaces dependent on a specific type of kernel
280or similar things like boot sequences.
281.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
282.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
283.It arm64 Ta aarch64 Ta aarch64
284.It amd64 Ta amd64 Ta amd64
285.It arm Ta arm Ta armv6, armv7
286.It i386 Ta i386 Ta i386
287.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le
288.It riscv Ta riscv Ta riscv64, riscv64sf
289.El
290.Ss Predefined Macros
291The compiler provides a number of predefined macros.
292Some of these provide architecture-specific details and are explained below.
293Other macros, including those required by the language standard, are not
294included here.
295.Pp
296The full set of predefined macros can be obtained with this command:
297.Bd -literal -offset indent
298cc -x c -dM -E /dev/null
299.Ed
300.Pp
301Common type size and endianness macros:
302.Bl -column -offset indent "BYTE_ORDER" "Meaning"
303.It Sy Macro Ta Sy Meaning
304.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
305.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
306.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
307.Dv PDP11_ENDIAN
308is not used on
309.Fx .
310.El
311.Pp
312Architecture-specific macros:
313.Bl -column -offset indent "Architecture" "Predefined macros"
314.It Sy Architecture Ta Sy Predefined macros
315.It aarch64     Ta Dv __aarch64__
316.It amd64       Ta Dv __amd64__ , Dv __x86_64__
317.It armv6       Ta Dv __arm__ , Dv __ARM_ARCH >= 6
318.It armv7       Ta Dv __arm__ , Dv __ARM_ARCH >= 7
319.It i386        Ta Dv __i386__
320.It powerpc     Ta Dv __powerpc__
321.It powerpcspe  Ta Dv __powerpc__ , Dv __SPE__
322.It powerpc64   Ta Dv __powerpc__ , Dv __powerpc64__
323.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__
324.It riscv64     Ta Dv __riscv , Dv __riscv_xlen == 64
325.It riscv64sf   Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __riscv_float_abi_soft
326.El
327.Pp
328Compilers may define additional variants of architecture-specific macros.
329The macros above are preferred for use in
330.Fx .
331.Ss Important Xr make 1 variables
332Most of the externally settable variables are defined in the
333.Xr build 7
334man page.
335These variables are not otherwise documented and are used extensively
336in the build system.
337.Bl -tag -width "MACHINE_CPUARCH"
338.It Dv MACHINE
339Represents the hardware platform.
340This is the same as the native platform's
341.Xr uname 1
342.Fl m
343output.
344It defines both the userland / kernel interface, as well as the
345bootloader / kernel interface.
346It should only be used in these contexts.
347Each CPU architecture may have multiple hardware platforms it supports
348where
349.Dv MACHINE
350differs among them.
351It is used to collect together all the files from
352.Xr config 8
353to build the kernel.
354It is often the same as
355.Dv MACHINE_ARCH
356just as one CPU architecture can be implemented by many different
357hardware platforms, one hardware platform may support multiple CPU
358architecture family members, though with different binaries.
359For example,
360.Dv MACHINE
361of i386 supported the IBM-AT hardware platform while the
362.Dv MACHINE
363of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
364hardware platforms.
365Both of these hardware platforms supported only the
366.Dv MACHINE_ARCH
367of i386 where they shared a common ABI, except for certain kernel /
368userland interfaces relating to underlying hardware platform
369differences in bus architecture, device enumeration and boot interface.
370Generally,
371.Dv MACHINE
372should only be used in src/sys and src/stand or in system imagers or
373installers.
374.It Dv MACHINE_ARCH
375Represents the CPU processor architecture.
376This is the same as the native platforms
377.Xr uname 1
378.Fl p
379output.
380It defines the CPU instruction family supported.
381It may also encode a variation in the byte ordering of multi-byte
382integers (endian).
383It may also encode a variation in the size of the integer or pointer.
384It may also encode a ISA revision.
385It may also encode hard versus soft floating point ABI and usage.
386It may also encode a variant ABI when the other factors do not
387uniquely define the ABI.
388It, along with
389.Dv MACHINE ,
390defines the ABI used by the system.
391Generally, the plain CPU name specifies the most common (or at least
392first) variant of the CPU.
393This is why powerpc and powerpc64 imply 'big endian' while 'armv6' and 'armv7'
394imply little endian.
395If we ever were to support the so-called x32 ABI (using 32-bit
396pointers on the amd64 architecture), it would most likely be encoded
397as amd64-x32.
398It is unfortunate that amd64 specifies the 64-bit evolution of the x86
399platform (it matches the 'first rule') as everybody else uses x86_64.
400There is no standard name for the processor: each OS selects its own
401conventions.
402.It Dv MACHINE_CPUARCH
403Represents the source location for a given
404.Dv MACHINE_ARCH .
405It is generally the common prefix for all the MACHINE_ARCH that
406share the same implementation, though 'riscv' breaks this rule.
407While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
408for them.
409The
410.Fx
411source base supports amd64 and i386 with two
412distinct source bases living in subdirectories named amd64 and i386
413(though behind the scenes there's some sharing that fits into this
414framework).
415.It Dv CPUTYPE
416Sets the flavor of
417.Dv MACHINE_ARCH
418to build.
419It is used to optimize the build for a specific CPU / core that the
420binaries run on.
421Generally, this does not change the ABI, though it can be a fine line
422between optimization for specific cases.
423.It Dv TARGET
424Used to set
425.Dv MACHINE
426in the top level Makefile for cross building.
427Unused outside of that scope.
428It is not passed down to the rest of the build.
429Makefiles outside of the top level should not use it at all (though
430some have their own private copy for hysterical raisons).
431.It Dv TARGET_ARCH
432Used to set
433.Dv MACHINE_ARCH
434by the top level Makefile for cross building.
435Like
436.Dv TARGET ,
437it is unused outside of that scope.
438.El
439.Sh SEE ALSO
440.Xr src.conf 5 ,
441.Xr build 7
442.Sh HISTORY
443An
444.Nm
445manual page appeared in
446.Fx 11.1 .
447