1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd November 7, 2019 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 10.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g., 72.Dv sparc64 , 73.Dv powerpc 74and AIM variants of 75.Dv powerpc64 , 76the kernel uses a separate address space. 77On other architectures, kernel and a user mode process share a 78single address space. 79The kernel is located at the highest addresses. 80.Pp 81On each architecture, the main user mode thread's stack starts near 82the highest user address and grows down. 83.Pp 84.Fx 85architecture support varies by release. 86This table shows the first 87.Fx 88release to support each architecture, and, for discontinued 89architectures, the final release. 90.Pp 91.Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release" 92.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 93.It aarch64 Ta 11.0 94.It alpha Ta 3.2 Ta 6.4 95.It amd64 Ta 5.1 96.It arm Ta 6.0 Ta 12.x 97.It armeb Ta 8.0 Ta 11.x 98.It armv6 Ta 10.0 99.It armv7 Ta 12.0 100.It ia64 Ta 5.0 Ta 10.4 101.It i386 Ta 1.0 102.It mips Ta 8.0 103.It mipsel Ta 9.0 104.It mipselhf Ta 12.0 105.It mipshf Ta 12.0 106.It mipsn32 Ta 9.0 107.It mips64 Ta 9.0 108.It mips64el Ta 9.0 109.It mips64elhf Ta 12.0 110.It mips64hf Ta 12.0 111.It pc98 Ta 2.2 Ta 11.x 112.It powerpc Ta 6.0 113.It powerpcspe Ta 12.0 114.It powerpc64 Ta 6.0 115.It riscv64 Ta 12.0 116.It riscv64sf Ta 12.0 117.It sparc64 Ta 5.0 Ta 12.x 118.El 119.Ss Type sizes 120All 121.Fx 122architectures use some variant of the ELF (see 123.Xr elf 5 ) 124.Sy Application Binary Interface 125(ABI) for the machine processor. 126All supported ABIs can be divided into two groups: 127.Bl -tag -width "Dv ILP32" 128.It Dv ILP32 129.Vt int , 130.Vt long , 131.Vt void * 132types machine representations all have 4-byte size. 133.It Dv LP64 134.Vt int 135type machine representation uses 4 bytes, 136while 137.Vt long 138and 139.Vt void * 140are 8 bytes. 141.El 142Compilers define the 143.Dv _LP64 144symbol when compiling for an 145.Dv LP64 146ABI. 147.Pp 148Some machines support more that one 149.Fx 150ABI. 151Typically these are 64-bit machines, where the 152.Dq native 153.Dv LP64 154execution environment is accompanied by the 155.Dq legacy 156.Dv ILP32 157environment, which was historical 32-bit predecessor for 64-bit evolution. 158Examples are: 159.Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart" 160.It Sy LP64 Ta Sy ILP32 counterpart 161.It Dv amd64 Ta Dv i386 162.It Dv powerpc64 Ta Dv powerpc 163.It Dv mips64* Ta Dv mips* 164.It Dv aarch64 Ta Dv armv6/armv7 165.El 166.Dv aarch64 167will support execution of 168.Dv armv6 169or 170.Dv armv7 171binaries if the CPU implements 172.Dv AArch32 173execution state, however 174.Dv armv5 175binaries aren't supported. 176.Pp 177On all supported architectures: 178.Bl -column -offset -indent "long long" "Size" 179.It Sy Type Ta Sy Size 180.It short Ta 2 181.It int Ta 4 182.It long Ta sizeof(void*) 183.It long long Ta 8 184.It float Ta 4 185.It double Ta 8 186.El 187Integers are represented in two's complement. 188Alignment of integer and pointer types is natural, that is, 189the address of the variable must be congruent to zero modulo the type size. 190Most ILP32 ABIs, except 191.Dv arm , 192require only 4-byte alignment for 64-bit integers. 193.Pp 194Machine-dependent type sizes: 195.Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t" 196.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 197.It aarch64 Ta 8 Ta 16 Ta 8 198.It amd64 Ta 8 Ta 16 Ta 8 199.It arm Ta 4 Ta 8 Ta 8 200.It armv6 Ta 4 Ta 8 Ta 8 201.It i386 Ta 4 Ta 12 Ta 4 202.It mips Ta 4 Ta 8 Ta 8 203.It mipsel Ta 4 Ta 8 Ta 8 204.It mipselhf Ta 4 Ta 8 Ta 8 205.It mipshf Ta 4 Ta 8 Ta 8 206.It mipsn32 Ta 4 Ta 8 Ta 8 207.It mips64 Ta 8 Ta 8 Ta 8 208.It mips64el Ta 8 Ta 8 Ta 8 209.It mips64elhf Ta 8 Ta 8 Ta 8 210.It mips64hf Ta 8 Ta 8 Ta 8 211.It powerpc Ta 4 Ta 8 Ta 8 212.It powerpcspe Ta 4 Ta 8 Ta 8 213.It powerpc64 Ta 8 Ta 8 Ta 8 214.It riscv64 Ta 8 Ta 16 Ta 8 215.It riscv64sf Ta 8 Ta 16 Ta 8 216.It sparc64 Ta 8 Ta 16 Ta 8 217.El 218.Pp 219.Sy time_t 220is 8 bytes on all supported architectures except i386. 221.Ss Endianness and Char Signedness 222.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" 223.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 224.It aarch64 Ta little Ta unsigned 225.It amd64 Ta little Ta signed 226.It arm Ta little Ta unsigned 227.It armv6 Ta little Ta unsigned 228.It armv7 Ta little Ta unsigned 229.It i386 Ta little Ta signed 230.It mips Ta big Ta signed 231.It mipsel Ta little Ta signed 232.It mipselhf Ta little Ta signed 233.It mipshf Ta big Ta signed 234.It mipsn32 Ta big Ta signed 235.It mips64 Ta big Ta signed 236.It mips64el Ta little Ta signed 237.It mips64elhf Ta little Ta signed 238.It mips64hf Ta big Ta signed 239.It powerpc Ta big Ta unsigned 240.It powerpcspe Ta big Ta unsigned 241.It powerpc64 Ta big Ta unsigned 242.It riscv64 Ta little Ta signed 243.It riscv64sf Ta little Ta signed 244.It sparc64 Ta big Ta signed 245.El 246.Ss Page Size 247.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" 248.It Sy Architecture Ta Sy Page Sizes 249.It aarch64 Ta 4K, 2M, 1G 250.It amd64 Ta 4K, 2M, 1G 251.It arm Ta 4K 252.It armv6 Ta 4K, 1M 253.It armv7 Ta 4K, 1M 254.It i386 Ta 4K, 2M (PAE), 4M 255.It mips Ta 4K 256.It mipsel Ta 4K 257.It mipselhf Ta 4K 258.It mipshf Ta 4K 259.It mipsn32 Ta 4K 260.It mips64 Ta 4K 261.It mips64el Ta 4K 262.It mips64elhf Ta 4K 263.It mips64hf Ta 4K 264.It powerpc Ta 4K 265.It powerpcspe Ta 4K 266.It powerpc64 Ta 4K 267.It riscv64 Ta 4K 268.It riscv64sf Ta 4K 269.It sparc64 Ta 8K 270.El 271.Ss Floating Point 272.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" 273.It Sy Architecture Ta Sy float, double Ta Sy long double 274.It aarch64 Ta hard Ta soft, quad precision 275.It amd64 Ta hard Ta hard, 80 bit 276.It arm Ta soft Ta soft, double precision 277.It armv6 Ta hard(1) Ta hard, double precision 278.It armv7 Ta hard(1) Ta hard, double precision 279.It i386 Ta hard Ta hard, 80 bit 280.It mips Ta soft Ta identical to double 281.It mipsel Ta soft Ta identical to double 282.It mipselhf Ta hard Ta identical to double 283.It mipshf Ta hard Ta identical to double 284.It mipsn32 Ta soft Ta identical to double 285.It mips64 Ta soft Ta identical to double 286.It mips64el Ta soft Ta identical to double 287.It mips64elhf Ta hard Ta identical to double 288.It mips64hf Ta hard Ta identical to double 289.It powerpc Ta hard Ta hard, double precision 290.It powerpcspe Ta hard Ta hard, double precision 291.It powerpc64 Ta hard Ta hard, double precision 292.It riscv64 Ta hard Ta hard, double precision 293.It riscv64sf Ta soft Ta soft, double precision 294.It sparc64 Ta hard Ta hard, quad precision 295.El 296.Pp 297(1) Prior to 298.Fx 11.0 , 299armv6 used the softfp ABI even though it supported only processors 300with a floating point unit. 301.Ss Default Tool Chain 302.Fx uses a variety of tool chain components for the supported CPU 303architectures: 304.Xr clang 1 305and 306.Xr ld.lld 1 307provided by the base system, 308GNU 309.Xr gcc 1 310and Binutils 311.Xr ld 1 , 312or an external toolchain compiler and linker provided by a port or package. 313This table shows the default tool chain for each architecture. 314.Bl -column -offset indent "Sy Architecture" "Sy Compiler" "Sy Linker" 315.It Sy Architecture Ta Sy Compiler Ta Sy Linker 316.It aarch64 Ta Clang Ta lld 317.It amd64 Ta Clang Ta lld 318.It arm Ta Clang Ta GNU ld 2.17.50 319.It armv6 Ta Clang Ta lld 320.It armv7 Ta Clang Ta lld 321.It i386 Ta Clang Ta lld 322.It mips Ta GCC 4.2.1 Ta GNU ld 2.17.50 323.It mipsel Ta GCC 4.2.1 Ta GNU ld 2.17.50 324.It mipselhf Ta GCC 4.2.1 Ta GNU ld 2.17.50 325.It mipshf Ta GCC 4.2.1 Ta GNU ld 2.17.50 326.It mipsn32 Ta GCC 4.2.1 Ta GNU ld 2.17.50 327.It mips64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 328.It mips64el Ta GCC 4.2.1 Ta GNU ld 2.17.50 329.It mips64elhf Ta GCC 4.2.1 Ta GNU ld 2.17.50 330.It mips64hf Ta GCC 4.2.1 Ta GNU ld 2.17.50 331.It powerpc Ta GCC 4.2.1 Ta GNU ld 2.17.50 332.It powerpcspe Ta GCC 4.2.1 Ta GNU ld 2.17.50 333.It powerpc64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 334.It riscv64 Ta GCC(1) Ta GNU ld(1) 335.It riscv64sf Ta GCC(1) Ta GNU ld(1) 336.It sparc64 Ta GCC 4.2.1 Ta GNU ld 2.17.50 337.El 338.Pp 339(1) External toolchain provided by ports/packages. 340.Pp 341Note that GCC 4.2.1 is deprecated, and scheduled for removal on 2020-03-31. 342Any CPU architectures not migrated by then 343(to either base system Clang or external toolchain) 344may be removed from the tree after that date. 345Unless the make variable 346.Dv MAKE_OBSOLETE_GCC 347is defined, make universe will not build mips, powerpc, nor sparc64 348architectures unless the xtoolchain binaries have been installed for 349the architecture. 350.Ss Predefined Macros 351The compiler provides a number of predefined macros. 352Some of these provide architecture-specific details and are explained below. 353Other macros, including those required by the language standard, are not 354included here. 355.Pp 356The full set of predefined macros can be obtained with this command: 357.Bd -literal -offset indent 358cc -x c -dM -E /dev/null 359.Ed 360.Pp 361Common type size and endianness macros: 362.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning" 363.It Sy Macro Ta Sy Meaning 364.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 365.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 366.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 367.Dv PDP11_ENDIAN 368is not used on 369.Fx . 370.El 371.Pp 372Architecture-specific macros: 373.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" 374.It Sy Architecture Ta Sy Predefined macros 375.It aarch64 Ta Dv __aarch64__ 376.It amd64 Ta Dv __amd64__, Dv __x86_64__ 377.It arm Ta Dv __arm__ 378.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 379.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7 380.It i386 Ta Dv __i386__ 381.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 382.It mipsel Ta Dv __mips__, Dv __mips_o32 383.It mipselhf Ta Dv __mips__, Dv __mips_o32 384.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 385.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 386.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 387.It mips64el Ta Dv __mips__, Dv __mips_n64 388.It mips64elhf Ta Dv __mips__, Dv __mips_n64 389.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 390.It powerpc Ta Dv __powerpc__ 391.It powerpcspe Ta Dv __powerpc__, Dv __SPE__ 392.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ 393.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 394.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 395.It sparc64 Ta Dv __sparc64__ 396.El 397.Pp 398Compilers may define additional variants of architecture-specific macros. 399The macros above are preferred for use in 400.Fx . 401.Ss Important Xr make 1 variables 402Most of the externally settable variables are defined in the 403.Xr build 7 404man page. 405These variables are not otherwise documented and are used extensively 406in the build system. 407.Bl -column -offset indent "Sy Variable" "Sy Meaning and usage" 408.It Dv MACHINE Represent the hardware platform. 409This is the same as the native platform's 410.Xr uname 1 411.Fl m 412output. 413It defines both the userland / kernel interface, as well as the 414bootloader / kernel interface. 415It should only be used in these contexts. 416Each CPU architecture may have multiple hardware platforms it supports 417where 418.Dv MACHINE 419differs among them. 420It is used to collect together all the files from 421.Xr config 8 422to build the kernel. 423It is often the same as 424.Dv MACHINE_ARCH 425just as one CPU architecture can be implemented by many different 426hardware platforms, one hardware platform may support multiple CPU 427architecture family members, though with different binaries. 428For example, 429.Dv MACHINE 430of i386 supported the IBM-AT hardware platform while the 431.Dv MACHINE 432of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 433hardware platforms. 434Both of these hardware platforms supported only the 435.Dv MACHINE_ARCH 436of i386 where they shared a common ABI, except for certain kernel / 437userland interfaces relating to underlying hardware platform 438differences in bus architecture, device enumeration and boot interface. 439Generally, 440.Dv MACHINE 441should only be used in src/sys and src/stand or in system imagers or 442installers. 443.It Dv MACHINE_ARCH Represents the CPU processor architecture. 444This is the same as the native platforms 445.Xr uname 1 446.Fl p 447output. 448It defines the CPU instruction family supported. 449It may also encode a variation in the byte ordering of multi-byte 450integers (endian). 451It may also encode a variation in the size of the integer or pointer. 452It may also encode a ISA revision. 453It may also encode hard versus soft floating point ABI and usage. 454It may also encode a variant ABI when the other factors do not 455uniquely define the ABI (e.g., MIPS' n32 ABI). 456It, along with 457.Dv MACHINE , 458defines the ABI used by the system. 459For example, the MIPS CPU processor family supports 9 different 460combinations encoding pointer size, endian and hard versus soft float (for 4618 combinations) as well as N32 (which only ever had one variation of 462all these). 463Generally, the plain CPU name specifies the most common (or at least 464first) variant of the CPU. 465This is why mips and mips64 imply 'big endian' while 'arm' and 'armv7' 466imply little endian. 467If we ever were to support the so-called x32 ABI (using 32-bit 468pointers on the amd64 architecture), it would most likely be encoded 469as amd64-x32. 470It is unfortunate that amd64 specifies the 64-bit evolution of the x86 471platform (it matches the 'first rule') as everybody else uses x86_64. 472There is no standard name for the processor: each OS selects its own 473conventions. 474.It Dv MACHINE_CPUARCH Represents the source location for a given 475.Dv MACHINE_ARCH . 476For example, 477.Dv MACHINE_CPUARCH 478is defined to be mips for all the flavors of mips that we support 479since we support them all with a shared set of sources. 480While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 481for them. 482The FreeBSD source base supports amd64 and i386 with two 483distinct source bases living in subdirectories named amd64 and i386 484(though behind the scenes there's some sharing that fits into this 485framework). 486.It Dv CPUTYPE Sets the flavor of 487.Dv MACHINE_ARCH 488to build. 489It is used to optimize the build for a specific CPU / core that the 490binaries run on. 491Generally, this does not change the ABI, though it can be a fine line 492between optimization for specific cases. 493.It Dv TARGET Used to set 494.Dv MACHINE 495in the top level Makefile for cross building. 496Unused outside of that scope. 497It is not passed down to the rest of the build. 498Makefiles outside of the top level should not use it at all (though 499some have their own private copy for hysterical raisons). 500.It Dv TARGET_ARCH Used to set 501.Dv MACHINE_ARCH 502by the top level Makefile for cross building. 503Like 504.Dv TARGET , it is unused outside of that scope. 505.El 506.Sh SEE ALSO 507.Xr src.conf 5 , 508.Xr build 7 509.Sh HISTORY 510An 511.Nm 512manual page appeared in 513.Fx 11.1 . 514