1.\" Copyright (c) 2016 The FreeBSD Foundation. All rights reserved. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd July 19, 2016 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Pp 39.Ss Type sizes 40On all supported architectures, 41.Bl -column -offset -indent "long long" "Size" 42.It Sy Type Ta Sy Size 43.It short Ta 2 44.It int Ta 4 45.It long Ta sizeof(void*) 46.It long long Ta 8 47.It float Ta 4 48.It double Ta 8 49.El 50.Bl -column -offset indent "Sy Architecture" "Sy sizeof(void *)" "Sy sizeof(long double)" 51.It Sy Architecture Ta Sy sizeof(void *) Ta Sy sizeof(long double) 52.It amd64 Ta 8 Ta 16 53.It arm Ta 4 Ta 8 54.It armeb Ta 4 Ta 8 55.It armv6 Ta 4 Ta 8 56.It arm64 Ta 8 Ta 16 57.It i386 Ta 4 Ta 12 58.It mips Ta 4 Ta 8 59.It mipsel Ta 4 Ta 8 60.It mipsn32 Ta 4 Ta 8 61.It mips64 Ta 8 Ta 8 62.It mips64el Ta 8 Ta 8 63.It powerpc Ta 4 Ta 8 64.It powerpc64 Ta 8 Ta 8 65.It riscv Ta 8 Ta 66.It sparc64 Ta 8 Ta 16 67.El 68.Ss Endianness and Char Signedness 69.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" 70.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 71.It amd64 Ta little Ta signed 72.It arm Ta little Ta unsigned 73.It armeb Ta big Ta unsigned 74.It armv6 Ta little Ta unsigned 75.It arm64 Ta little Ta unsigned 76.It i386 Ta little Ta signed 77.It mips Ta big Ta signed 78.It mipsel Ta little Ta signed 79.It mipsn32 Ta big Ta signed 80.It mips64 Ta big Ta signed 81.It mips64el Ta little Ta signed 82.It powerpc Ta big Ta unsigned 83.It powerpc64 Ta big Ta unsigned 84.It riscv Ta little Ta signed 85.It sparc64 Ta big Ta signed 86.El 87.Ss Page Size 88.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" 89.It Sy Architecture Ta Sy Page Sizes 90.It amd64 Ta 4K, 2M, 1G 91.It arm Ta 4K 92.It armeb Ta 4K 93.It armv6 Ta 4K, 1M 94.It arm64 Ta 4K, 2M, 1G 95.It i386 Ta 4K, 2M (PAE), 4M 96.It mips Ta 4K 97.It mipsel Ta 4K 98.It mipsn32 Ta 4K 99.It mips64 Ta 4K 100.It mips64el Ta 4K 101.It powerpc Ta 4K 102.It powerpc64 Ta 4K 103.It riscv Ta 4K 104.It sparc64 Ta 8K 105.El 106.Ss Floating Point 107.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" 108.It Sy Architecture Ta Sy float, double Ta Sy long double 109.It amd64 Ta hard Ta hard, 80 bit 110.It arm Ta soft Ta soft, double precision 111.It armeb Ta soft Ta soft, double precision 112.It armv6 Ta hard Ta hard, double precision 113.It arm64 Ta hard Ta soft, quad precision 114.It i386 Ta hard Ta hard, 80 bit 115.It mips Ta soft Ta identical to double 116.It mipsel Ta soft Ta identical to double 117.It mipsn32 Ta soft Ta identical to double 118.It mips64 Ta soft Ta identical to double 119.It mips64el Ta soft Ta identical to double 120.It powerpc Ta hard Ta hard, double precision 121.It powerpc64 Ta hard Ta hard, double precision 122.It riscv Ta 123.It sparc64 Ta hard Ta hard, quad precision 124.El 125.Ss Predefined Macros 126The compiler provides a number of predefined macros. 127Some of these provide architecture-specific details and are explained below. 128Other macros, including those required by the language standard, are not 129included here. 130.Pp 131The full set of predefined macros can be obtained with this command: 132.Bd -literal -offset indent 133cc -x c -Dm -E /dev/null 134.Ed 135.Pp 136Common type size and endianness macros: 137.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning" 138.It Sy Macro Ta Sy Meaning 139.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 140.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 141.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 142.Dv PDP11_ENDIAN 143is not used on 144.Fx . 145.El 146.Pp 147Architecture-specific macros: 148.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" 149.It Sy Architecture Ta Sy Predefined macros 150.It amd64 Ta Dv __amd64__, Dv __x86_64__ 151.It arm Ta Dv __arm__ 152.It armeb Ta Dv __arm__ 153.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 154.It arm64 Ta Dv __aarch64__ 155.It i386 Ta Dv __i386__ 156.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 157.It mipsel Ta Dv __mips__, Dv __mips_o32 158.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 159.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 160.It mips64el Ta Dv __mips__, Dv __mips_n64 161.It powerpc Ta Dv __powerpc__ 162.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ 163.It riscv Ta Dv __riscv__, Dv __riscv64 164.It sparc64 Ta Dv __sparc64__ 165.El 166.Sh SEE ALSO 167.Xr src.conf 5 , 168.Xr build 7 169.Sh HISTORY 170An 171.Nm 172manual page appeared in 173.Fx 12 . 174