1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd March 8, 2020 30.Dt ARCH 7 31.Os 32.Sh NAME 33.Nm arch 34.Nd Architecture-specific details 35.Sh DESCRIPTION 36Differences between CPU architectures and platforms supported by 37.Fx . 38.Ss Introduction 39This document is a quick reference of key ABI details of 40.Fx 41architecture ports. 42For full details consult the processor-specific ABI supplement 43documentation. 44.Pp 45If not explicitly mentioned, sizes are in bytes. 46The architecture details in this document apply to 47.Fx 11.0 48and later, unless otherwise noted. 49.Pp 50.Fx 51uses a flat address space. 52Variables of types 53.Vt unsigned long , 54.Vt uintptr_t , 55and 56.Vt size_t 57and pointers all have the same representation. 58.Pp 59In order to maximize compatibility with future pointer integrity mechanisms, 60manipulations of pointers as integers should be performed via 61.Vt uintptr_t 62or 63.Vt intptr_t 64and no other types. 65In particular, 66.Vt long 67and 68.Vt ptrdiff_t 69should be avoided. 70.Pp 71On some architectures, e.g., 72.Dv powerpc 73and AIM variants of 74.Dv powerpc64 , 75the kernel uses a separate address space. 76On other architectures, kernel and a user mode process share a 77single address space. 78The kernel is located at the highest addresses. 79.Pp 80On each architecture, the main user mode thread's stack starts near 81the highest user address and grows down. 82.Pp 83.Fx 84architecture support varies by release. 85This table shows the first 86.Fx 87release to support each architecture, and, for discontinued 88architectures, the final release. 89.Pp 90.Bl -column -offset indent "Architecture" "Initial Release" "Final Release" 91.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 92.It aarch64 Ta 11.0 93.It alpha Ta 3.2 Ta 6.4 94.It amd64 Ta 5.1 95.It arm Ta 6.0 Ta 12.x 96.It armeb Ta 8.0 Ta 11.x 97.It armv6 Ta 10.0 98.It armv7 Ta 12.0 99.It ia64 Ta 5.0 Ta 10.4 100.It i386 Ta 1.0 101.It mips Ta 8.0 102.It mipsel Ta 9.0 103.It mipselhf Ta 12.0 104.It mipshf Ta 12.0 105.It mipsn32 Ta 9.0 106.It mips64 Ta 9.0 107.It mips64el Ta 9.0 108.It mips64elhf Ta 12.0 109.It mips64hf Ta 12.0 110.It pc98 Ta 2.2 Ta 11.x 111.It powerpc Ta 6.0 112.It powerpcspe Ta 12.0 113.It powerpc64 Ta 6.0 114.It riscv64 Ta 12.0 115.It riscv64sf Ta 12.0 116.It sparc64 Ta 5.0 Ta 12.x 117.El 118.Ss Type sizes 119All 120.Fx 121architectures use some variant of the ELF (see 122.Xr elf 5 ) 123.Sy Application Binary Interface 124(ABI) for the machine processor. 125All supported ABIs can be divided into two groups: 126.Bl -tag -width "Dv ILP32" 127.It Dv ILP32 128.Vt int , 129.Vt long , 130.Vt void * 131types machine representations all have 4-byte size. 132.It Dv LP64 133.Vt int 134type machine representation uses 4 bytes, 135while 136.Vt long 137and 138.Vt void * 139are 8 bytes. 140.El 141.Pp 142Some machines support more than one 143.Fx 144ABI. 145Typically these are 64-bit machines, where the 146.Dq native 147.Dv LP64 148execution environment is accompanied by the 149.Dq legacy 150.Dv ILP32 151environment, which was the historical 32-bit predecessor for 64-bit evolution. 152Examples are: 153.Bl -column -offset indent "powerpc64" "ILP32 counterpart" 154.It Sy LP64 Ta Sy ILP32 counterpart 155.It Dv amd64 Ta Dv i386 156.It Dv powerpc64 Ta Dv powerpc 157.It Dv mips64* Ta Dv mips* 158.It Dv aarch64 Ta Dv armv6/armv7 159.El 160.Pp 161.Dv aarch64 162will support execution of 163.Dv armv6 164or 165.Dv armv7 166binaries if the CPU implements 167.Dv AArch32 168execution state, however 169.Dv armv5 170binaries aren't supported. 171.Pp 172On all supported architectures: 173.Bl -column -offset -indent "long long" "Size" 174.It Sy Type Ta Sy Size 175.It short Ta 2 176.It int Ta 4 177.It long Ta sizeof(void*) 178.It long long Ta 8 179.It float Ta 4 180.It double Ta 8 181.El 182.Pp 183Integers are represented in two's complement. 184Alignment of integer and pointer types is natural, that is, 185the address of the variable must be congruent to zero modulo the type size. 186Most ILP32 ABIs, except 187.Dv arm , 188require only 4-byte alignment for 64-bit integers. 189.Pp 190Machine-dependent type sizes: 191.Bl -column -offset indent "Architecture" "void *" "long double" "time_t" 192.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 193.It aarch64 Ta 8 Ta 16 Ta 8 194.It amd64 Ta 8 Ta 16 Ta 8 195.It armv6 Ta 4 Ta 8 Ta 8 196.It armv7 Ta 4 Ta 8 Ta 8 197.It i386 Ta 4 Ta 12 Ta 4 198.It mips Ta 4 Ta 8 Ta 8 199.It mipsel Ta 4 Ta 8 Ta 8 200.It mipselhf Ta 4 Ta 8 Ta 8 201.It mipshf Ta 4 Ta 8 Ta 8 202.It mipsn32 Ta 4 Ta 8 Ta 8 203.It mips64 Ta 8 Ta 8 Ta 8 204.It mips64el Ta 8 Ta 8 Ta 8 205.It mips64elhf Ta 8 Ta 8 Ta 8 206.It mips64hf Ta 8 Ta 8 Ta 8 207.It powerpc Ta 4 Ta 8 Ta 8 208.It powerpcspe Ta 4 Ta 8 Ta 8 209.It powerpc64 Ta 8 Ta 8 Ta 8 210.It riscv64 Ta 8 Ta 16 Ta 8 211.It riscv64sf Ta 8 Ta 16 Ta 8 212.El 213.Pp 214.Sy time_t 215is 8 bytes on all supported architectures except i386. 216.Ss Endianness and Char Signedness 217.Bl -column -offset indent "Architecture" "Endianness" "char Signedness" 218.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 219.It aarch64 Ta little Ta unsigned 220.It amd64 Ta little Ta signed 221.It armv6 Ta little Ta unsigned 222.It armv7 Ta little Ta unsigned 223.It i386 Ta little Ta signed 224.It mips Ta big Ta signed 225.It mipsel Ta little Ta signed 226.It mipselhf Ta little Ta signed 227.It mipshf Ta big Ta signed 228.It mipsn32 Ta big Ta signed 229.It mips64 Ta big Ta signed 230.It mips64el Ta little Ta signed 231.It mips64elhf Ta little Ta signed 232.It mips64hf Ta big Ta signed 233.It powerpc Ta big Ta unsigned 234.It powerpcspe Ta big Ta unsigned 235.It powerpc64 Ta big Ta unsigned 236.It riscv64 Ta little Ta signed 237.It riscv64sf Ta little Ta signed 238.El 239.Ss Page Size 240.Bl -column -offset indent "Architecture" "Page Sizes" 241.It Sy Architecture Ta Sy Page Sizes 242.It aarch64 Ta 4K, 2M, 1G 243.It amd64 Ta 4K, 2M, 1G 244.It armv6 Ta 4K, 1M 245.It armv7 Ta 4K, 1M 246.It i386 Ta 4K, 2M (PAE), 4M 247.It mips Ta 4K 248.It mipsel Ta 4K 249.It mipselhf Ta 4K 250.It mipshf Ta 4K 251.It mipsn32 Ta 4K 252.It mips64 Ta 4K 253.It mips64el Ta 4K 254.It mips64elhf Ta 4K 255.It mips64hf Ta 4K 256.It powerpc Ta 4K 257.It powerpcspe Ta 4K 258.It powerpc64 Ta 4K 259.It riscv64 Ta 4K 260.It riscv64sf Ta 4K 261.El 262.Ss Floating Point 263.Bl -column -offset indent "Architecture" "float, double" "long double" 264.It Sy Architecture Ta Sy float, double Ta Sy long double 265.It aarch64 Ta hard Ta soft, quad precision 266.It amd64 Ta hard Ta hard, 80 bit 267.It armv6 Ta hard Ta hard, double precision 268.It armv7 Ta hard Ta hard, double precision 269.It i386 Ta hard Ta hard, 80 bit 270.It mips Ta soft Ta identical to double 271.It mipsel Ta soft Ta identical to double 272.It mipselhf Ta hard Ta identical to double 273.It mipshf Ta hard Ta identical to double 274.It mipsn32 Ta soft Ta identical to double 275.It mips64 Ta soft Ta identical to double 276.It mips64el Ta soft Ta identical to double 277.It mips64elhf Ta hard Ta identical to double 278.It mips64hf Ta hard Ta identical to double 279.It powerpc Ta hard Ta hard, double precision 280.It powerpcspe Ta hard Ta hard, double precision 281.It powerpc64 Ta hard Ta hard, double precision 282.It riscv64 Ta hard Ta hard, double precision 283.It riscv64sf Ta soft Ta soft, double precision 284.El 285.Ss Default Tool Chain 286.Fx uses a variety of tool chain components for the supported CPU 287architectures: 288.Xr clang 1 289and 290.Xr ld.lld 1 291provided by the base system, 292GNU 293.Xr gcc 1 294and Binutils 295.Xr ld 1 , 296or an external toolchain compiler and linker provided by a port or package. 297This table shows the default tool chain for each architecture. 298.Bl -column -offset indent "Architecture" "Compiler" "Linker" 299.It Sy Architecture Ta Sy Compiler Ta Sy Linker 300.It aarch64 Ta Clang Ta lld 301.It amd64 Ta Clang Ta lld 302.It armv6 Ta Clang Ta lld 303.It armv7 Ta Clang Ta lld 304.It i386 Ta Clang Ta lld 305.It mips Ta GCC(1) Ta GNU ld(1) 306.It mipsel Ta GCC(1) Ta GNU ld(1) 307.It mipselhf Ta GCC(1) Ta GNU ld(1) 308.It mipshf Ta GCC(1) Ta GNU ld(1) 309.It mipsn32 Ta GCC(1) Ta GNU ld(1) 310.It mips64 Ta GCC(1) Ta GNU ld(1) 311.It mips64el Ta GCC(1) Ta GNU ld(1) 312.It mips64elhf Ta GCC(1) Ta GNU ld(1) 313.It mips64hf Ta GCC(1) Ta GNU ld(1) 314.It powerpc Ta Clang Ta GNU ld 2.17.50 315.It powerpcspe Ta Clang Ta GNU ld 2.17.50 316.It powerpc64 Ta Clang Ta lld 317.It riscv64 Ta Clang Ta lld 318.It riscv64sf Ta Clang Ta lld 319.El 320.Pp 321(1) External toolchain provided by ports/packages. 322.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE 323.Dv MACHINE_CPUARCH 324should be preferred in Makefiles when the generic 325architecture is being tested. 326.Dv MACHINE_ARCH 327should be preferred when there is something specific to a particular type of 328architecture where there is a choice of many, or could be a choice of many. 329Use 330.Dv MACHINE 331when referring to the kernel, interfaces dependent on a specific type of kernel 332or similar things like boot sequences. 333.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH" 334.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH 335.It arm64 Ta aarch64 Ta aarch64 336.It amd64 Ta amd64 Ta amd64 337.It arm Ta arm Ta armv6, armv7 338.It i386 Ta i386 Ta i386 339.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32 340.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64 341.It riscv Ta riscv Ta riscv64, riscv64sf 342.El 343.Ss Predefined Macros 344The compiler provides a number of predefined macros. 345Some of these provide architecture-specific details and are explained below. 346Other macros, including those required by the language standard, are not 347included here. 348.Pp 349The full set of predefined macros can be obtained with this command: 350.Bd -literal -offset indent 351cc -x c -dM -E /dev/null 352.Ed 353.Pp 354Common type size and endianness macros: 355.Bl -column -offset indent "BYTE_ORDER" "Meaning" 356.It Sy Macro Ta Sy Meaning 357.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 358.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 359.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 360.Dv PDP11_ENDIAN 361is not used on 362.Fx . 363.El 364.Pp 365Architecture-specific macros: 366.Bl -column -offset indent "Architecture" "Predefined macros" 367.It Sy Architecture Ta Sy Predefined macros 368.It aarch64 Ta Dv __aarch64__ 369.It amd64 Ta Dv __amd64__, Dv __x86_64__ 370.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 371.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7 372.It i386 Ta Dv __i386__ 373.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 374.It mipsel Ta Dv __mips__, Dv __mips_o32 375.It mipselhf Ta Dv __mips__, Dv __mips_o32 376.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 377.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32 378.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 379.It mips64el Ta Dv __mips__, Dv __mips_n64 380.It mips64elhf Ta Dv __mips__, Dv __mips_n64 381.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64 382.It powerpc Ta Dv __powerpc__ 383.It powerpcspe Ta Dv __powerpc__, Dv __SPE__ 384.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ 385.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 386.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 387.El 388.Pp 389Compilers may define additional variants of architecture-specific macros. 390The macros above are preferred for use in 391.Fx . 392.Ss Important Xr make 1 variables 393Most of the externally settable variables are defined in the 394.Xr build 7 395man page. 396These variables are not otherwise documented and are used extensively 397in the build system. 398.Bl -tag -width "MACHINE_CPUARCH" 399.It Dv MACHINE 400Represents the hardware platform. 401This is the same as the native platform's 402.Xr uname 1 403.Fl m 404output. 405It defines both the userland / kernel interface, as well as the 406bootloader / kernel interface. 407It should only be used in these contexts. 408Each CPU architecture may have multiple hardware platforms it supports 409where 410.Dv MACHINE 411differs among them. 412It is used to collect together all the files from 413.Xr config 8 414to build the kernel. 415It is often the same as 416.Dv MACHINE_ARCH 417just as one CPU architecture can be implemented by many different 418hardware platforms, one hardware platform may support multiple CPU 419architecture family members, though with different binaries. 420For example, 421.Dv MACHINE 422of i386 supported the IBM-AT hardware platform while the 423.Dv MACHINE 424of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 425hardware platforms. 426Both of these hardware platforms supported only the 427.Dv MACHINE_ARCH 428of i386 where they shared a common ABI, except for certain kernel / 429userland interfaces relating to underlying hardware platform 430differences in bus architecture, device enumeration and boot interface. 431Generally, 432.Dv MACHINE 433should only be used in src/sys and src/stand or in system imagers or 434installers. 435.It Dv MACHINE_ARCH 436Represents the CPU processor architecture. 437This is the same as the native platforms 438.Xr uname 1 439.Fl p 440output. 441It defines the CPU instruction family supported. 442It may also encode a variation in the byte ordering of multi-byte 443integers (endian). 444It may also encode a variation in the size of the integer or pointer. 445It may also encode a ISA revision. 446It may also encode hard versus soft floating point ABI and usage. 447It may also encode a variant ABI when the other factors do not 448uniquely define the ABI (e.g., MIPS' n32 ABI). 449It, along with 450.Dv MACHINE , 451defines the ABI used by the system. 452For example, the MIPS CPU processor family supports 9 different 453combinations encoding pointer size, endian and hard versus soft float (for 4548 combinations) as well as N32 (which only ever had one variation of 455all these). 456Generally, the plain CPU name specifies the most common (or at least 457first) variant of the CPU. 458This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7' 459imply little endian. 460If we ever were to support the so-called x32 ABI (using 32-bit 461pointers on the amd64 architecture), it would most likely be encoded 462as amd64-x32. 463It is unfortunate that amd64 specifies the 64-bit evolution of the x86 464platform (it matches the 'first rule') as everybody else uses x86_64. 465There is no standard name for the processor: each OS selects its own 466conventions. 467.It Dv MACHINE_CPUARCH 468Represents the source location for a given 469.Dv MACHINE_ARCH . 470It is generally the common prefix for all the MACHINE_ARCH that 471share the same implementation, though 'riscv' breaks this rule. 472For example, 473.Dv MACHINE_CPUARCH 474is defined to be mips for all the flavors of mips that we support 475since we support them all with a shared set of sources. 476While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 477for them. 478The FreeBSD source base supports amd64 and i386 with two 479distinct source bases living in subdirectories named amd64 and i386 480(though behind the scenes there's some sharing that fits into this 481framework). 482.It Dv CPUTYPE 483Sets the flavor of 484.Dv MACHINE_ARCH 485to build. 486It is used to optimize the build for a specific CPU / core that the 487binaries run on. 488Generally, this does not change the ABI, though it can be a fine line 489between optimization for specific cases. 490.It Dv TARGET 491Used to set 492.Dv MACHINE 493in the top level Makefile for cross building. 494Unused outside of that scope. 495It is not passed down to the rest of the build. 496Makefiles outside of the top level should not use it at all (though 497some have their own private copy for hysterical raisons). 498.It Dv TARGET_ARCH 499Used to set 500.Dv MACHINE_ARCH 501by the top level Makefile for cross building. 502Like 503.Dv TARGET , 504it is unused outside of that scope. 505.El 506.Sh SEE ALSO 507.Xr src.conf 5 , 508.Xr build 7 509.Sh HISTORY 510An 511.Nm 512manual page appeared in 513.Fx 11.1 . 514