1.\" Copyright (c) 2016-2017 The FreeBSD Foundation. 2.\" 3.\" This documentation was created by Ed Maste under sponsorship of 4.\" The FreeBSD Foundation. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE. 26.\" 27.Dd October 1, 2025 28.Dt ARCH 7 29.Os 30.Sh NAME 31.Nm arch 32.Nd Architecture-specific details 33.Sh DESCRIPTION 34Differences between CPU architectures and platforms supported by 35.Fx . 36.Ss Introduction 37This document is a quick reference of key ABI details of 38.Fx 39architecture ports. 40For full details consult the processor-specific ABI supplement 41documentation. 42.Pp 43If not explicitly mentioned, sizes are in bytes. 44The architecture details in this document apply to 45.Fx 13.0 46and later, unless otherwise noted. 47.Pp 48.Fx 49uses a flat address space. 50Variables of types 51.Vt unsigned long , 52.Vt uintptr_t , 53and 54.Vt size_t 55and pointers all have the same representation. 56.Pp 57In order to maximize compatibility with future pointer integrity mechanisms, 58manipulations of pointers as integers should be performed via 59.Vt uintptr_t 60or 61.Vt intptr_t 62and no other types. 63In particular, 64.Vt long 65and 66.Vt ptrdiff_t 67should be avoided. 68.Pp 69On some architectures, e.g., 70AIM variants of 71.Dv powerpc64 , 72the kernel uses a separate address space. 73On other architectures, kernel and a user mode process share a 74single address space. 75The kernel is located at the highest addresses. 76.Pp 77On each architecture, the main user mode thread's stack starts near 78the highest user address and grows down. 79.Pp 80.Fx 81architecture support varies by release. 82This table shows currently supported CPU architectures along with the first 83.Fx 84release to support each architecture. 85.Bl -column -offset indent "Architecture" "Initial Release" 86.It Sy Architecture Ta Sy Initial Release 87.It aarch64 Ta 11.0 88.It amd64 Ta 5.1 89.It armv7 Ta 12.0 90.It powerpc64 Ta 9.0 91.It powerpc64le Ta 13.0 92.It riscv64 Ta 12.0 93.El 94.Pp 95Discontinued architectures are shown in the following table. 96.Bl -column -offset indent "Architecture" "Initial Release" "Final Release" 97.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release 98.It alpha Ta 3.2 Ta 6.4 99.It arm Ta 6.0 Ta 12.4 100.It armeb Ta 8.0 Ta 11.4 101.It armv6 Ta 10.0 Ta 14.x 102.It ia64 Ta 5.0 Ta 10.4 103.It i386 Ta 1.0 Ta 14.x 104.It mips Ta 8.0 Ta 13.5 105.It mipsel Ta 9.0 Ta 13.5 106.It mipselhf Ta 12.0 Ta 13.5 107.It mipshf Ta 12.0 Ta 13.5 108.It mipsn32 Ta 9.0 Ta 13.5 109.It mips64 Ta 9.0 Ta 13.5 110.It mips64el Ta 9.0 Ta 13.5 111.It mips64elhf Ta 12.0 Ta 13.5 112.It mips64hf Ta 12.0 Ta 13.5 113.It pc98 Ta 2.2 Ta 11.4 114.It powerpc Ta 6.0 Ta 14.x 115.It powerpcspe Ta 12.0 Ta 14.x 116.It riscv64sf Ta 12.0 Ta 13.5 117.It sparc64 Ta 5.0 Ta 12.4 118.El 119.Ss Type sizes 120All 121.Fx 122architectures use some variant of the ELF (see 123.Xr elf 5 ) 124.Sy Application Binary Interface 125(ABI) for the machine processor. 126All supported ABIs can be divided into two groups: 127.Bl -tag -width "Dv ILP32" 128.It Dv ILP32 129.Vt int , 130.Vt long , 131.Vt void * 132types machine representations all have 4-byte size. 133.It Dv LP64 134.Vt int 135type machine representation uses 4 bytes, 136while 137.Vt long 138and 139.Vt void * 140are 8 bytes. 141.El 142.Pp 143Some machines support more than one 144.Fx 145ABI. 146Typically these are 64-bit machines, where the 147.Dq native 148.Dv LP64 149execution environment is accompanied by the 150.Dq legacy 151.Dv ILP32 152environment, which was the historical 32-bit predecessor for 64-bit evolution. 153Examples are: 154.Bl -column -offset indent "powerpc64" "ILP32 counterpart" 155.It Sy LP64 Ta Sy ILP32 counterpart 156.It Dv amd64 Ta Dv i386 157.It Dv powerpc64 Ta Dv powerpc 158.It Dv aarch64 Ta Dv armv7 159.El 160.Pp 161.Dv aarch64 162will support execution of 163.Dv armv7 164binaries if the CPU implements 165.Dv AArch32 166execution state. 167Binaries targeting 168.Dv armv6 169and earlier are no longer supported by 170.Fx . 171.Pp 172On all supported architectures: 173.Bl -column -offset indent "long long" "Size" 174.It Sy Type Ta Sy Size 175.It short Ta 2 176.It int Ta 4 177.It long Ta sizeof(void*) 178.It long long Ta 8 179.It float Ta 4 180.It double Ta 8 181.El 182.Pp 183Integers are represented in two's complement. 184Alignment of integer and pointer types is natural, that is, 185the address of the variable must be congruent to zero modulo the type size. 186The sole exception is that 187.Dv i386 188requires only 4-byte alignment for 64-bit integers. 189.Pp 190Machine-dependent type sizes: 191.Bl -column -offset indent "Architecture" "void *" "long double" "time_t" 192.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t 193.It aarch64 Ta 8 Ta 16 Ta 8 194.It amd64 Ta 8 Ta 16 Ta 8 195.It armv7 Ta 4 Ta 8 Ta 8 196.It i386 Ta 4 Ta 12 Ta 4 197.It powerpc Ta 4 Ta 8 Ta 8 198.It powerpcspe Ta 4 Ta 8 Ta 8 199.It powerpc64 Ta 8 Ta 8 Ta 8 200.It powerpc64le Ta 8 Ta 8 Ta 8 201.It riscv64 Ta 8 Ta 16 Ta 8 202.El 203.Pp 204.Sy time_t 205is 8 bytes on all supported architectures except i386. 206.Ss Endianness and Char Signedness 207.Bl -column -offset indent "Architecture" "Endianness" "char Signedness" 208.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness 209.It aarch64 Ta little Ta unsigned 210.It amd64 Ta little Ta signed 211.It armv7 Ta little Ta unsigned 212.It i386 Ta little Ta signed 213.It powerpc Ta big Ta unsigned 214.It powerpcspe Ta big Ta unsigned 215.It powerpc64 Ta big Ta unsigned 216.It powerpc64le Ta little Ta unsigned 217.It riscv64 Ta little Ta signed 218.El 219.Ss Page Size 220.Bl -column -offset indent "Architecture" "Page Sizes" 221.It Sy Architecture Ta Sy Page Sizes 222.It aarch64 Ta 4K, 64K, 2M, 1G 223.It amd64 Ta 4K, 2M, 1G 224.It armv7 Ta 4K, 1M 225.It i386 Ta 4K, 2M (PAE), 4M 226.It powerpc Ta 4K 227.It powerpcspe Ta 4K 228.It powerpc64 Ta 4K 229.It powerpc64le Ta 4K 230.It riscv64 Ta 4K, 2M, 1G 231.El 232.Ss User Address Space Layout 233.Bl -column -offset indent "riscv64 (Sv48)" "0x0001000000000000" "NNNU" 234.It Sy Architecture Ta Sy Maximum Address Ta Sy Address Space Size 235.It aarch64 Ta 0x0001000000000000 Ta 256TiB 236.It amd64 (LA48) Ta 0x0000800000000000 Ta 128TiB 237.It amd64 (LA57) Ta 0x0100000000000000 Ta 64PiB 238.It armv7 Ta 0xbfc00000 Ta 3GiB 239.It i386 Ta 0xffc00000 Ta 4GiB 240.It powerpc Ta 0xfffff000 Ta 4GiB 241.It powerpcspe Ta 0x7ffff000 Ta 2GiB 242.It powerpc64 Ta 0x000fffffc0000000 Ta 4PiB 243.It powerpc64le Ta 0x000fffffc0000000 Ta 4PiB 244.It riscv64 (Sv39) Ta 0x0000004000000000 Ta 256GiB 245.It riscv64 (Sv48) Ta 0x0000800000000000 Ta 128TiB 246.El 247.Pp 248The layout of a process' address space can be queried via the 249.Dv KERN_PROC_VM_LAYOUT 250.Xr sysctl 3 251MIB. 252.Pp 253Historically, amd64 CPUs were limited to a 48-bit virtual address space. 254Newer CPUs support 5-level page tables, which extend the significant bits of 255addresses to 57 bits (LA57 mode). 256The address space layout is determined by the CPU's support for LA57. 257Setting the 258.Sy vm.pmap.la57 259tunable to 0 forces the system into 4-level paging mode, even on hardware that 260supports 5-level paging. 261In this mode, all processes get a 48-bit address space. 262The 263.Sy vm.pmap.prefer_la48_uva 264tunable determines whether processes running on a LA57 system are limited to 265a 48-bit address space by default. 266Some applications make use of unused upper bits in pointer values to store 267information, and thus implicitly assume they are running in LA48 mode. 268To avoid breaking compatibility, all processes run in LA48 mode by default. 269The 270.Xr elfctl 1 271utility can be used to request LA48 or LA57 mode for specific executables. 272Similarly, 273.Xr proccontrol 1 274can be used to configure the address space layout when executing a process. 275.Pp 276The RISC-V specification permits 3-level (Sv39), 4-level (Sv48), and 2775-level (Sv57) page tables. 278Hardware is only required to implement Sv39; implementations which support 279Sv48 must also support Sv39, and implementations which support Sv57 must also 280support Sv48. 281The 282.Sy vm.pmap.mode 283tunable can be used to select the layout. 284.Fx 285currently supports Sv39 and Sv48 and defaults to using Sv39. 286.Ss Floating Point 287.Bl -column -offset indent "Architecture" "float, double" "long double" 288.It Sy Architecture Ta Sy float, double Ta Sy long double 289.It aarch64 Ta hard Ta soft, quad precision 290.It amd64 Ta hard Ta hard, 80 bit 291.It armv7 Ta hard Ta hard, double precision 292.It i386 Ta hard Ta hard, 80 bit 293.It powerpc Ta hard Ta hard, double precision 294.It powerpcspe Ta hard Ta hard, double precision 295.It powerpc64 Ta hard Ta hard, double precision 296.It powerpc64le Ta hard Ta hard, double precision 297.It riscv64 Ta hard Ta hard, quad precision 298.El 299.Ss Default Tool Chain 300.Fx 301uses 302.Xr clang 1 303as the default compiler on all supported CPU architectures, 304LLVM's 305.Xr ld.lld 1 306as the default linker, and 307LLVM binary utilities such as 308.Xr objcopy 1 309and 310.Xr readelf 1 . 311.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE 312.Dv MACHINE_CPUARCH 313should be preferred in Makefiles when the generic 314architecture is being tested. 315.Dv MACHINE_ARCH 316should be preferred when there is something specific to a particular type of 317architecture where there is a choice of many, or could be a choice of many. 318Use 319.Dv MACHINE 320when referring to the kernel, interfaces dependent on a specific type of kernel 321or similar things like boot sequences. 322.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH" 323.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH 324.It arm64 Ta aarch64 Ta aarch64 325.It amd64 Ta amd64 Ta amd64 326.It arm Ta arm Ta armv7 327.It i386 Ta i386 Ta i386 328.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le 329.It riscv Ta riscv Ta riscv64 330.El 331.Ss Predefined Macros 332The compiler provides a number of predefined macros. 333Some of these provide architecture-specific details and are explained below. 334Other macros, including those required by the language standard, are not 335included here. 336.Pp 337The full set of predefined macros can be obtained with this command: 338.Bd -literal -offset indent 339cc -x c -dM -E /dev/null 340.Ed 341.Pp 342Common type size and endianness macros: 343.Bl -column -offset indent "BYTE_ORDER" "Meaning" 344.It Sy Macro Ta Sy Meaning 345.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int 346.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer 347.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN . 348.El 349.Pp 350Architecture-specific macros: 351.Bl -column -offset indent "Architecture" "Predefined macros" 352.It Sy Architecture Ta Sy Predefined macros 353.It aarch64 Ta Dv __aarch64__ 354.It amd64 Ta Dv __amd64__ , Dv __x86_64__ 355.It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7 356.It i386 Ta Dv __i386__ 357.It powerpc Ta Dv __powerpc__ 358.It powerpcspe Ta Dv __powerpc__ , Dv __SPE__ 359.It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__ 360.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__ 361.It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64 362.El 363.Pp 364Compilers may define additional variants of architecture-specific macros. 365The macros above are preferred for use in 366.Fx . 367.Ss Important Xr make 1 variables 368Most of the externally settable variables are defined in the 369.Xr build 7 370man page. 371These variables are not otherwise documented and are used extensively 372in the build system. 373.Bl -tag -width "MACHINE_CPUARCH" 374.It Dv MACHINE 375Represents the hardware platform. 376This is the same as the native platform's 377.Xr uname 1 378.Fl m 379output. 380It defines both the userland / kernel interface, as well as the 381bootloader / kernel interface. 382It should only be used in these contexts. 383Each CPU architecture may have multiple hardware platforms it supports 384where 385.Dv MACHINE 386differs among them. 387It is used to collect together all the files from 388.Xr config 8 389to build the kernel. 390It is often the same as 391.Dv MACHINE_ARCH 392just as one CPU architecture can be implemented by many different 393hardware platforms, one hardware platform may support multiple CPU 394architecture family members, though with different binaries. 395For example, 396.Dv MACHINE 397of i386 supported the IBM-AT hardware platform while the 398.Dv MACHINE 399of pc98 supported the Japanese company NEC's PC-9801 and PC-9821 400hardware platforms. 401Both of these hardware platforms supported only the 402.Dv MACHINE_ARCH 403of i386 where they shared a common ABI, except for certain kernel / 404userland interfaces relating to underlying hardware platform 405differences in bus architecture, device enumeration and boot interface. 406Generally, 407.Dv MACHINE 408should only be used in src/sys and src/stand or in system imagers or 409installers. 410.It Dv MACHINE_ARCH 411Represents the CPU processor architecture. 412This is the same as the native platforms 413.Xr uname 1 414.Fl p 415output. 416It defines the CPU instruction family supported. 417It may also encode a variation in the byte ordering of multi-byte 418integers (endian). 419It may also encode a variation in the size of the integer or pointer. 420It may also encode a ISA revision. 421It may also encode hard versus soft floating point ABI and usage. 422It may also encode a variant ABI when the other factors do not 423uniquely define the ABI. 424It, along with 425.Dv MACHINE , 426defines the ABI used by the system. 427Generally, the plain CPU name specifies the most common (or at least 428first) variant of the CPU. 429This is why powerpc and powerpc64 imply 'big endian' while armv7 and aarch64 430imply little endian. 431If we ever were to support the so-called x32 ABI (using 32-bit 432pointers on the amd64 architecture), it would most likely be encoded 433as amd64-x32. 434It is unfortunate that amd64 specifies the 64-bit evolution of the x86 platform 435(it matches the 'first rule') as almost everybody else uses x86_64. 436The 437.Fx 438port was so early, it predated processor name standardization after Intel joined 439the market. 440At the time, each OS selected its own conventions. 441Backwards compatibility means it is not easy to change to the consensus name. 442.It Dv MACHINE_CPUARCH 443Represents the source location for a given 444.Dv MACHINE_ARCH . 445It is generally the common prefix for all the MACHINE_ARCH that 446share the same implementation, though 'riscv' breaks this rule. 447While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 448for them. 449The 450.Fx 451source base supports amd64 and i386 with two 452distinct source bases living in subdirectories named amd64 and i386 453(though behind the scenes there's some sharing that fits into this 454framework). 455.It Dv CPUTYPE 456Sets the flavor of 457.Dv MACHINE_ARCH 458to build. 459It is used to optimize the build for a specific CPU / core that the 460binaries run on. 461Generally, this does not change the ABI, though it can be a fine line 462between optimization for specific cases. 463.It Dv TARGET 464Used to set 465.Dv MACHINE 466in the top level Makefile for cross building. 467Unused outside of that scope. 468It is not passed down to the rest of the build. 469Makefiles outside of the top level should not use it at all (though 470some have their own private copy for historical reasons). 471.It Dv TARGET_ARCH 472Used to set 473.Dv MACHINE_ARCH 474by the top level Makefile for cross building. 475Like 476.Dv TARGET , 477it is unused outside of that scope. 478.El 479.Sh SEE ALSO 480.Xr elfctl 1 , 481.Xr proccontrol 1 , 482.Xr sysctl 3 , 483.Xr src.conf 5 , 484.Xr build 7 , 485.Xr simd 7 486.Sh HISTORY 487An 488.Nm 489manual page appeared in 490.Fx 11.1 . 491