1.\" Copyright (c) 1997, 1998 2.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 3. All advertising materials mentioning features or use of this software 13.\" must display the following acknowledgement: 14.\" This product includes software developed by Bill Paul. 15.\" 4. Neither the name of the author nor the names of any co-contributors 16.\" may be used to endorse or promote products derived from this software 17.\" without specific prior written permission. 18.\" 19.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 20.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 23.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29.\" THE POSSIBILITY OF SUCH DAMAGE. 30.\" 31.\" $FreeBSD$ 32.\" 33.Dd November 22, 1998 34.Dt VR 4 35.Os FreeBSD 36.Sh NAME 37.Nm vr 38.Nd 39VIA Technologies VT3043 and VT86C100A ethernet device driver 40.Sh SYNOPSIS 41.Cd "device miibus" 42.Cd "device vr" 43.Sh DESCRIPTION 44The 45.Nm 46driver provides support for PCI ethernet adapters and embedded 47controllers based on the VIA Technologies VT3043 Rhine I and 48VT86C100A Rhine II fast ethernet controller chips. This includes 49the D-Link DFE530-TX, the Hawking Technologies PN102TX, the 50AOpen/Acer ALN-320, and various other commodity fast ethernet 51cards. 52.Pp 53The VIA Rhine chips use bus master DMA and have a descriptor layout 54designed to resemble that of the DEC 21x4x "tulip" chips. The register 55layout is different however and the receive filter in the Rhine chips 56is much simpler and is programmed through registers rather than by 57downloading a special setup frame through the transmit DMA engine. 58Transmit and receive DMA buffers must be longword 59aligned. The Rhine chips are meant to be interfaced with external 60physical layer devices via an MII bus. They support both 6110 and 100Mbps speeds in either full or half duplex. 62.Pp 63The 64.Nm 65driver supports the following media types: 66.Pp 67.Bl -tag -width xxxxxxxxxxxxxxxxxxxx 68.It autoselect 69Enable autoselection of the media type and options. 70The user can manually override 71the autoselected mode by adding media options to the 72.Pa /etc/rc.conf 73file. 74.It 10baseT/UTP 75Set 10Mbps operation. The 76.Ar mediaopt 77option can also be used to select either 78.Ar full-duplex 79or 80.Ar half-duplex modes. 81.It 100baseTX 82Set 100Mbps (fast ethernet) operation. The 83.Ar mediaopt 84option can also be used to select either 85.Ar full-duplex 86or 87.Ar half-duplex 88modes. 89.El 90.Pp 91The 92.Nm 93driver supports the following media options: 94.Pp 95.Bl -tag -width xxxxxxxxxxxxxxxxxxxx 96.It full-duplex 97Force full duplex operation 98.It half-duplex 99Force half duplex operation. 100.El 101.Pp 102Note that the 100baseTX media type is only available if supported 103by the adapter. 104For more information on configuring this device, see 105.Xr ifconfig 8 . 106.Sh DIAGNOSTICS 107.Bl -diag 108.It "vr%d: couldn't map memory" 109A fatal initialization error has occurred. 110.It "vr%d: couldn't map interrupt" 111A fatal initialization error has occurred. 112.It "vr%d: watchdog timeout" 113The device has stopped responding to the network, or there is a problem with 114the network connection (cable). 115.It "vr%d: no memory for rx list" 116The driver failed to allocate an mbuf for the receiver ring. 117.It "vr%d: no memory for tx list" 118The driver failed to allocate an mbuf for the transmitter ring when 119allocating a pad buffer or collapsing an mbuf chain into a cluster. 120.It "vr%d: chip is in D3 power state -- setting to D0" 121This message applies only to adapters which support power 122management. Some operating systems place the controller in low power 123mode when shutting down, and some PCI BIOSes fail to bring the chip 124out of this state before configuring it. The controller loses all of 125its PCI configuration in the D3 state, so if the BIOS does not set 126it back to full power mode in time, it won't be able to configure it 127correctly. The driver tries to detect this condition and bring 128the adapter back to the D0 (full power) state, but this may not be 129enough to return the driver to a fully operational condition. If 130you see this message at boot time and the driver fails to attach 131the device as a network interface, you will have to perform second 132warm boot to have the device properly configured. 133.Pp 134Note that this condition only occurs when warm booting from another 135operating system. If you power down your system prior to booting 136.Fx , 137the card should be configured correctly. 138.El 139.Sh SEE ALSO 140.Xr arp 4 , 141.Xr netintro 4 , 142.Xr ifconfig 8 , 143.Xr ng_ether 8 144.Rs 145.%T The VIA Technologies VT86C100A data sheet 146.%O http://www.via.com.tw 147.Re 148.Sh HISTORY 149The 150.Nm 151device driver first appeared in 152.Fx 3.0 . 153.Sh AUTHORS 154The 155.Nm 156driver was written by 157.An Bill Paul Aq wpaul@ctr.columbia.edu . 158.Sh BUGS 159The 160.Nm 161driver always copies transmit mbuf chains into longword-aligned 162buffers prior to transmission in order to pacify the Rhine chips. 163If buffers are not aligned correctly, the chip will round the 164supplied buffer address and begin DMAing from the wrong location. 165This buffer copying impairs transmit performance on slower systems but can't 166be avoided. On faster machines (e.g. a Pentium II), the performance 167impact is much less noticable. 168