1.\" Copyright (c) 1997 2.\" Steve Passe <fsmp@FreeBSD.org>. All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. The name of the developer may NOT be used to endorse or promote products 10.\" derived from this software without specific prior written permission. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd January 4, 2019 25.Dt SMP 4 26.Os 27.Sh NAME 28.Nm SMP 29.Nd description of the FreeBSD Symmetric Multi-Processor kernel 30.Sh SYNOPSIS 31.Cd options SMP 32.Sh DESCRIPTION 33The 34.Nm 35kernel implements symmetric multi-processor support. 36.Pp 37.Nm 38support can be disabled by setting the loader tunable 39.Va kern.smp.disabled 40to 1. 41.Pp 42The number of CPUs detected by the system is available in 43the read-only sysctl variable 44.Va hw.ncpu . 45.Pp 46The number of online threads per CPU core is available in the read-only sysctl 47variable 48.Va kern.smp.threads_per_core . 49The number of physical CPU cores detected by the system is available in the 50read-only sysctl variable 51.Va kern.smp.cores . 52.Pp 53.Fx 54allows specific CPUs on a multi-processor system to be disabled. 55This can be done using the 56.Va hint.lapic.X.disabled 57tunable, where X is the APIC ID of a CPU. 58Setting this tunable to 1 will result in the corresponding CPU being 59disabled. 60.Pp 61.Fx 62supports simultaneous multithreading on x86 and powerpc platforms. 63On x86, the logical CPUs can be disabled by setting the 64.Va machdep.hyperthreading_allowed 65tunable to zero. 66.Pp 67The 68.Xr sched_ule 4 69scheduler implements CPU topology detection and adjusts the scheduling 70algorithms to make better use of modern multi-core CPUs. 71The sysctl variable 72.Va kern.sched.topology_spec 73reflects the detected CPU hardware in a parsable XML format. 74The top level XML tag is <groups>, which encloses one or more <group> tags 75containing data about individual CPU groups. 76A CPU group contains CPUs that are detected to be "close" together, usually 77by being cores in a single multi-core processor. 78Attributes available in a <group> tag are "level", corresponding to the 79nesting level of the CPU group and "cache-level", corresponding to the 80level of CPU caches shared by the CPUs in the group. 81The <group> tag contains the <cpu> and <flags> tags. 82The <cpu> tag describes CPUs in the group. 83Its attributes are "count", corresponding to the number of CPUs in the 84group and "mask", corresponding to the integer binary mask in which 85each bit position set to 1 signifies a CPU belonging to the group. 86The contents (CDATA) of the <cpu> tag is the comma-delimited list 87of CPU indexes (derived from the "mask" attribute). 88The <flags> tag contains special tags (if any) describing the relation 89of the CPUs in the group. 90The possible flags are currently "HTT" and "SMT", corresponding to 91the various implementations of hardware multithreading. 92An example topology_spec output for a system consisting of 93two quad-core processors is: 94.Bd -literal 95<groups> 96 <group level="1" cache-level="0"> 97 <cpu count="8" mask="0xff">0, 1, 2, 3, 4, 5, 6, 7</cpu> 98 <flags></flags> 99 <children> 100 <group level="2" cache-level="0"> 101 <cpu count="4" mask="0xf">0, 1, 2, 3</cpu> 102 <flags></flags> 103 </group> 104 <group level="2" cache-level="0"> 105 <cpu count="4" mask="0xf0">4, 5, 6, 7</cpu> 106 <flags></flags> 107 </group> 108 </children> 109 </group> 110</groups> 111.Ed 112.Pp 113This information is used internally by the kernel to schedule related 114tasks on CPUs that are closely grouped together. 115.Sh COMPATIBILITY 116Support for multi-processor systems is present for all Tier-1 and Tier-2 117architectures on 118.Fx . 119Currently, this includes x86, powerpc, mips, arm and arm64. 120Support is enabled using 121.Cd options SMP . 122It is permissible to use the SMP kernel configuration on non-SMP hardware. 123.Sh I386 NOTES 124For i386 systems, the 125.Nm 126kernel supports motherboards that follow the Intel MP specification, 127version 1.4. 128In addition to 129.Cd options SMP , 130i386 also requires 131.Cd device apic . 132The 133.Xr mptable 1 134command may be used to view the status of multi-processor support. 135.Sh SEE ALSO 136.Xr cpuset 1 , 137.Xr mptable 1 , 138.Xr sched_4bsd 4 , 139.Xr sched_ule 4 , 140.Xr loader 8 , 141.Xr sysctl 8 , 142.Xr condvar 9 , 143.Xr msleep 9 , 144.Xr mtx_pool 9 , 145.Xr mutex 9 , 146.Xr rwlock 9 , 147.Xr sema 9 , 148.Xr sx 9 149.Sh HISTORY 150The 151.Nm 152kernel's early history is not (properly) recorded. 153It was developed 154in a separate CVS branch until April 26, 1997, at which point it was 155merged into 3.0-current. 156By this date 3.0-current had already been 157merged with Lite2 kernel code. 158.Pp 159.Fx 5.0 160introduced support for a host of new synchronization primitives, and 161a move towards fine-grained kernel locking rather than reliance on 162a Giant kernel lock. 163The SMPng Project relied heavily on the support of BSDi, who provided 164reference source code from the fine-grained SMP implementation found 165in 166.Bsx . 167.Pp 168.Fx 5.0 169also introduced support for SMP on the sparc64 architecture. 170.Sh AUTHORS 171.An Steve Passe Aq Mt fsmp@FreeBSD.org 172.Sh CAVEATS 173The 174.Va kern.smp.threads_per_core 175and 176.Va kern.smp.cores 177sysctl variables are provided as a best-effort guess. 178If an architecture or platform adds SMT and 179.Fx 180has not yet implemented detection, the reported values may be inaccurate. 181In this case, 182.Va kern.smp.threads_per_core 183will report 184.Dv 1 185and 186.Va kern.smp.cores 187will report the same value as 188.Va hw.ncpu . 189