1.\" Copyright (c) 1997 2.\" Steve Passe <fsmp@FreeBSD.org>. All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. The name of the developer may NOT be used to endorse or promote products 10.\" derived from this software without specific prior written permission. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd May 7, 2008 27.Dt SMP 4 28.Os 29.Sh NAME 30.Nm SMP 31.Nd description of the FreeBSD Symmetric Multi-Processor kernel 32.Sh SYNOPSIS 33.Cd options SMP 34.Sh DESCRIPTION 35The 36.Nm 37kernel implements symmetric multi-processor support. 38.Sh COMPATIBILITY 39Support for multi-processor systems is present for all Tier-1 40architectures on 41.Fx . 42Currently, this includes amd64, i386, ia64, and sparc64. 43Support is enabled using 44.Cd options SMP . 45It is permissible to use the SMP kernel configuration on non-SMP equipped 46motherboards. 47.Sh I386 NOTES 48For i386 systems, the 49.Nm 50kernel supports motherboards that follow the Intel MP specification, 51version 1.4. 52In addition to 53.Cd options SMP , 54i386 also requires 55.Cd device apic . 56The 57.Xr mptable 1 58command may be used to view the status of multi-processor support. 59.Pp 60The number of CPUs detected by the system is available in 61the read-only sysctl variable 62.Va hw.ncpu . 63.Pp 64.Fx 65allows specific CPUs on a multi-processor system to be disabled. 66The sysctl variable 67.Va machdep.hlt_cpus 68is an integer bitmask denoting CPUs to halt, counting from 0. 69Setting a bit to 1 will result in the corresponding CPU being 70disabled. 71.Pp 72The 73.Xr sched_ule 4 74scheduler implements CPU topology detection and adjusts the scheduling 75algorithms to make better use of modern multi-core CPUs. 76The sysctl variable 77.Va kern.sched.topology_spec 78reflects the detected CPU hardware in a parsable XML format. 79The top level XML tag is <groups>, which encloses one or more <group> tags 80containing data about individual CPU groups. 81A CPU group contains CPUs that are detected to be "close" together, usually 82by being cores in a single multi-core processor. 83Attributes available in a <group> tag are "level", corresponding to the 84nesting level of the CPU group and "cache-level", corresponding to the 85level of CPU caches shared by the CPUs in the group. 86The <group> tag contains the <cpu> and <flags> tags. 87The <cpu> tag describes CPUs in the group. 88Its attributes are "count", corresponding to the number of CPUs in the 89group and "mask", corresponding to the integer binary mask in which 90each bit position set to 1 signifies a CPU belonging to the group. 91The contents (CDATA) of the <cpu> tag is the comma-delimited list 92of CPU indexes (derived from the "mask" attribute). 93The <flags> tag contains special tags (if any) describing the relation 94of the CPUs in the group. 95The possible flags are currently "HTT" and "SMT", corresponding to 96the various implementations of hardware multithreading. 97An example topology_spec output for a system consisting of 98two quad-core processors is: 99.Bd -literal 100<groups> 101 <group level="1" cache-level="0"> 102 <cpu count="8" mask="0xff">0, 1, 2, 3, 4, 5, 6, 7</cpu> 103 <flags></flags> 104 <children> 105 <group level="2" cache-level="0"> 106 <cpu count="4" mask="0xf">0, 1, 2, 3</cpu> 107 <flags></flags> 108 </group> 109 <group level="2" cache-level="0"> 110 <cpu count="4" mask="0xf0">4, 5, 6, 7</cpu> 111 <flags></flags> 112 </group> 113 </children> 114 </group> 115</groups> 116.Ed 117.Pp 118This information is used internally by the kernel to schedule related 119tasks on CPUs that are closely grouped together. 120.Pp 121.Fx 122supports hyperthreading on Intel CPU's on the i386 and AMD64 platforms. 123Since using logical CPUs can cause performance penalties under certain loads, 124the logical CPUs can be disabled by setting the 125.Va machdep.hlt_logical_cpus 126sysctl to one. 127Note that this operation is different from the mechanism used by the 128.Xr cpuset 1 . 129.Sh SEE ALSO 130.Xr mptable 1 , 131.Xr sysctl 8 , 132.Xr condvar 9 , 133.Xr msleep 9 , 134.Xr mtx_pool 9 , 135.Xr mutex 9 , 136.Xr sema 9 , 137.Xr sx 9 , 138.Xr rwlock 9 , 139.Xr sched_4bsd 4 , 140.Xr sched_ule 4 , 141.Xr cpuset 1 142.Sh HISTORY 143The 144.Nm 145kernel's early history is not (properly) recorded. 146It was developed 147in a separate CVS branch until April 26, 1997, at which point it was 148merged into 3.0-current. 149By this date 3.0-current had already been 150merged with Lite2 kernel code. 151.Pp 152.Fx 5.0 153introduced support for a host of new synchronization primitives, and 154a move towards fine-grained kernel locking rather than reliance on 155a Giant kernel lock. 156The SMPng Project relied heavily on the support of BSDi, who provided 157reference source code from the fine-grained SMP implementation found 158in 159.Bsx . 160.Pp 161.Fx 5.0 162also introduced support for SMP on the ia64 and sparc64 architectures. 163.Sh AUTHORS 164.An Steve Passe Aq fsmp@FreeBSD.org 165