1.\" Copyright (c) 1997 2.\" Steve Passe <fsmp@FreeBSD.org>. All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. The name of the developer may NOT be used to endorse or promote products 10.\" derived from this software without specific prior written permission. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd January 6, 2018 27.Dt SMP 4 28.Os 29.Sh NAME 30.Nm SMP 31.Nd description of the FreeBSD Symmetric Multi-Processor kernel 32.Sh SYNOPSIS 33.Cd options SMP 34.Sh DESCRIPTION 35The 36.Nm 37kernel implements symmetric multi-processor support. 38.Sh COMPATIBILITY 39Support for multi-processor systems is present for all Tier-1 40architectures on 41.Fx . 42Currently, this includes amd64, i386 and sparc64. 43Support is enabled using 44.Cd options SMP . 45It is permissible to use the SMP kernel configuration on non-SMP equipped 46motherboards. 47.Sh I386 NOTES 48For i386 systems, the 49.Nm 50kernel supports motherboards that follow the Intel MP specification, 51version 1.4. 52In addition to 53.Cd options SMP , 54i386 also requires 55.Cd device apic . 56The 57.Xr mptable 1 58command may be used to view the status of multi-processor support. 59.Pp 60.Nm 61support can be disabled by setting the loader tunable 62.Va kern.smp.disabled 63to 1. 64.Pp 65The number of CPUs detected by the system is available in 66the read-only sysctl variable 67.Va hw.ncpu . 68.Pp 69.Fx 70allows specific CPUs on a multi-processor system to be disabled. 71This can be done using the 72.Va hint.lapic.X.disabled 73tunable, where X is the APIC ID of a CPU. 74Setting this tunable to 1 will result in the corresponding CPU being 75disabled. 76.Pp 77The 78.Xr sched_ule 4 79scheduler implements CPU topology detection and adjusts the scheduling 80algorithms to make better use of modern multi-core CPUs. 81The sysctl variable 82.Va kern.sched.topology_spec 83reflects the detected CPU hardware in a parsable XML format. 84The top level XML tag is <groups>, which encloses one or more <group> tags 85containing data about individual CPU groups. 86A CPU group contains CPUs that are detected to be "close" together, usually 87by being cores in a single multi-core processor. 88Attributes available in a <group> tag are "level", corresponding to the 89nesting level of the CPU group and "cache-level", corresponding to the 90level of CPU caches shared by the CPUs in the group. 91The <group> tag contains the <cpu> and <flags> tags. 92The <cpu> tag describes CPUs in the group. 93Its attributes are "count", corresponding to the number of CPUs in the 94group and "mask", corresponding to the integer binary mask in which 95each bit position set to 1 signifies a CPU belonging to the group. 96The contents (CDATA) of the <cpu> tag is the comma-delimited list 97of CPU indexes (derived from the "mask" attribute). 98The <flags> tag contains special tags (if any) describing the relation 99of the CPUs in the group. 100The possible flags are currently "HTT" and "SMT", corresponding to 101the various implementations of hardware multithreading. 102An example topology_spec output for a system consisting of 103two quad-core processors is: 104.Bd -literal 105<groups> 106 <group level="1" cache-level="0"> 107 <cpu count="8" mask="0xff">0, 1, 2, 3, 4, 5, 6, 7</cpu> 108 <flags></flags> 109 <children> 110 <group level="2" cache-level="0"> 111 <cpu count="4" mask="0xf">0, 1, 2, 3</cpu> 112 <flags></flags> 113 </group> 114 <group level="2" cache-level="0"> 115 <cpu count="4" mask="0xf0">4, 5, 6, 7</cpu> 116 <flags></flags> 117 </group> 118 </children> 119 </group> 120</groups> 121.Ed 122.Pp 123This information is used internally by the kernel to schedule related 124tasks on CPUs that are closely grouped together. 125.Pp 126.Fx 127supports hyperthreading on Intel CPU's on the i386 and AMD64 platforms. 128Because using logical CPUs can cause performance penalties under certain loads, 129the logical CPUs can be disabled by setting the 130.Va machdep.hyperthreading_allowed 131tunable to zero. 132.Sh SEE ALSO 133.Xr cpuset 1 , 134.Xr mptable 1 , 135.Xr sched_4bsd 4 , 136.Xr sched_ule 4 , 137.Xr loader 8 , 138.Xr sysctl 8 , 139.Xr condvar 9 , 140.Xr msleep 9 , 141.Xr mtx_pool 9 , 142.Xr mutex 9 , 143.Xr rwlock 9 , 144.Xr sema 9 , 145.Xr sx 9 146.Sh HISTORY 147The 148.Nm 149kernel's early history is not (properly) recorded. 150It was developed 151in a separate CVS branch until April 26, 1997, at which point it was 152merged into 3.0-current. 153By this date 3.0-current had already been 154merged with Lite2 kernel code. 155.Pp 156.Fx 5.0 157introduced support for a host of new synchronization primitives, and 158a move towards fine-grained kernel locking rather than reliance on 159a Giant kernel lock. 160The SMPng Project relied heavily on the support of BSDi, who provided 161reference source code from the fine-grained SMP implementation found 162in 163.Bsx . 164.Pp 165.Fx 5.0 166also introduced support for SMP on the sparc64 architecture. 167.Sh AUTHORS 168.An Steve Passe Aq Mt fsmp@FreeBSD.org 169