1.\" Copyright (c) 1998, 1999, Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd March 5, 1998 28.Dt PPC 4 29.Os 30.Sh NAME 31.Nm ppc 32.Nd Parallel Port Chipset driver 33.Sh SYNOPSIS 34.Cd "device ppc" 35.Pp 36In 37.Pa /boot/device.hints : 38.Cd hint.ppc.0.at="isa" 39.Cd hint.ppc.0.irq="7" 40.Pp 41For one or more PPBUS busses: 42.Cd "device ppbus" 43.Sh DESCRIPTION 44The 45.Nm 46driver provides low level support to various parallel port chipsets for the 47.Xr ppbus 4 48system. 49.Pp 50During the probe phase, 51.Nm 52detects parallel port chipsets and initializes 53private data according to their operating mode: COMPATIBLE, 54NIBBLE, PS/2, EPP, ECP and other mixed modes. 55If a mode is provided at startup through the 56.Va flags 57variable of the boot 58interface, the operating mode of the chipset is forced according to 59.Va flags 60and the hardware supported modes. 61.Pp 62During the attach phase, 63.Nm 64allocates a ppbus structure, initializes it and calls the ppbus 65attach function. 66.Ss Supported flags 67.Bl -item -offset indent 68.It 69bits 0-3: chipset forced mode(s) 70.Bd -literal 71PPB_COMPATIBLE 0x0 /* Centronics compatible mode */ 72PPB_NIBBLE 0x1 /* reverse 4 bit mode */ 73PPB_PS2 0x2 /* PS/2 byte mode */ 74PPB_EPP 0x4 /* EPP mode, 32 bit */ 75PPB_ECP 0x8 /* ECP mode */ 76.Ed 77.Pp 78And any mixed values. 79.It 80bit 4: EPP protocol (0 EPP 1.9, 1 EPP 1.7) 81.It 82bit 5: activate IRQ (1 IRQ disabled, 0 IRQ enabled) 83.It 84bit 6: disable chipset specific detection 85.It 86bit 7: disable FIFO detection 87.El 88.Ss Supported chipsets 89Some parallel port chipsets are explicitly supported: 90detection and initialisation code has been written according to 91their datasheets. 92.Bl -bullet -offset indent 93.It 94SMC FDC37C665GT and FDC37C666GT chipsets 95.It 96Natsemi PC873xx-family (PC87332 and PC87306) 97.It 98Winbond W83877xx-family (W83877F and W83877AF) 99.It 100SMC-like chipsets with mixed modes (see 101.Xr ppbus 4 ) 102.El 103.Ss Adding support to a new chipset 104You may want to add support for the newest chipset your motherboard was 105sold with. 106For the ISA bus, just retrieve the specs of the chipset and write the 107corresponding 108.Fn ppc_mychipset_detect "" 109function. 110Then add an entry to the general purpose 111.Fn ppc_detect "" 112function. 113.Pp 114Your 115.Fn ppc_mychipset_detect "" 116function should ensure that if the mode field of the 117.Va flags 118boot variable is not null, then the operating 119mode is forced to the given mode and no other mode is available and 120ppb->ppb_avm field contains the available modes of the chipset. 121.Sh SEE ALSO 122.Xr ppbus 4 , 123.Xr ppi 4 , 124.Xr device.hints 5 125.Sh BUGS 126The chipset detection process may corrupt your chipset configuration. 127You may 128disable chipset specific detection by using the above flags. 129.Sh HISTORY 130The 131.Nm 132manual page first appeared in 133.Fx 3.0 . 134.Sh AUTHORS 135This manual page was written by 136.An Nicolas Souchu . 137