1.\" Copyright (c) 1998, 1999, Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd March 5, 1998 26.Dt PPC 4 27.Os 28.Sh NAME 29.Nm ppc 30.Nd Parallel Port Chipset driver 31.Sh SYNOPSIS 32.Cd "device ppc" 33.Pp 34In 35.Pa /boot/device.hints : 36.Cd hint.ppc.0.at="isa" 37.Cd hint.ppc.0.irq="7" 38.Pp 39For one or more PPBUS busses: 40.Cd "device ppbus" 41.Sh DESCRIPTION 42The 43.Nm 44driver provides low level support to various parallel port chipsets for the 45.Xr ppbus 4 46system. 47.Pp 48During the probe phase, 49.Nm 50detects parallel port chipsets and initializes 51private data according to their operating mode: COMPATIBLE, 52NIBBLE, PS/2, EPP, ECP and other mixed modes. 53If a mode is provided at startup through the 54.Va flags 55variable of the boot 56interface, the operating mode of the chipset is forced according to 57.Va flags 58and the hardware supported modes. 59.Pp 60During the attach phase, 61.Nm 62allocates a ppbus structure, initializes it and calls the ppbus 63attach function. 64.Ss Supported flags 65.Bl -item -offset indent 66.It 67bits 0-3: chipset forced mode(s) 68.Bd -literal 69PPB_COMPATIBLE 0x0 /* Centronics compatible mode */ 70PPB_NIBBLE 0x1 /* reverse 4 bit mode */ 71PPB_PS2 0x2 /* PS/2 byte mode */ 72PPB_EPP 0x4 /* EPP mode, 32 bit */ 73PPB_ECP 0x8 /* ECP mode */ 74.Ed 75.Pp 76And any mixed values. 77.It 78bit 4: EPP protocol (0 EPP 1.9, 1 EPP 1.7) 79.It 80bit 5: activate IRQ (1 IRQ disabled, 0 IRQ enabled) 81.It 82bit 6: disable chipset specific detection 83.It 84bit 7: disable FIFO detection 85.El 86.Ss Supported chipsets 87Some parallel port chipsets are explicitly supported: 88detection and initialisation code has been written according to 89their datasheets. 90.Bl -bullet -offset indent 91.It 92SMC FDC37C665GT and FDC37C666GT chipsets 93.It 94Natsemi PC873xx-family (PC87332 and PC87306) 95.It 96Winbond W83877xx-family (W83877F and W83877AF) 97.It 98SMC-like chipsets with mixed modes (see 99.Xr ppbus 4 ) 100.El 101.Ss Adding support to a new chipset 102You may want to add support for the newest chipset your motherboard was 103sold with. 104For the ISA bus, just retrieve the specs of the chipset and write the 105corresponding 106.Fn ppc_mychipset_detect "" 107function. 108Then add an entry to the general purpose 109.Fn ppc_detect "" 110function. 111.Pp 112Your 113.Fn ppc_mychipset_detect "" 114function should ensure that if the mode field of the 115.Va flags 116boot variable is not null, then the operating 117mode is forced to the given mode and no other mode is available and 118ppb->ppb_avm field contains the available modes of the chipset. 119.Sh SEE ALSO 120.Xr ppbus 4 , 121.Xr ppi 4 , 122.Xr device.hints 5 123.Sh HISTORY 124The 125.Nm 126manual page first appeared in 127.Fx 3.0 . 128.Sh AUTHORS 129This manual page was written by 130.An Nicolas Souchu . 131.Sh BUGS 132The chipset detection process may corrupt your chipset configuration. 133You may 134disable chipset specific detection by using the above flags. 135