1.\" Copyright (c) 2005 Christian Brueffer 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd July 29, 2020 26.Dt PADLOCK 4 27.Os 28.Sh NAME 29.Nm padlock 30.Nd "driver for the cryptographic functions and RNG in VIA C3, C7 and Eden processors" 31.Sh SYNOPSIS 32To compile this driver into the kernel, 33place the following lines in your 34kernel configuration file: 35.Bd -ragged -offset indent 36.Cd "device crypto" 37.Cd "device padlock" 38.Ed 39.Pp 40Alternatively, to load the driver as a 41module at boot time, place the following line in 42.Xr loader.conf 5 : 43.Bd -literal -offset indent 44padlock_load="YES" 45.Ed 46.Sh DESCRIPTION 47The C3 and Eden processor series from VIA include hardware acceleration for 48AES. 49The C7 series includes hardware acceleration for AES, SHA1, SHA256 and RSA. 50All of the above processor series include a hardware random number generator. 51.Pp 52The 53.Nm 54driver registers itself to accelerate AES operations and, if available, HMAC/SHA1 55and HMAC/SHA256 for 56.Xr crypto 4 . 57It also registers itself to accelerate other HMAC algorithms, although 58there is no hardware acceleration for those algorithms. 59This is only needed so 60.Nm 61can work with 62.Xr ipsec 4 . 63.Pp 64The hardware random number generator supplies data for the kernel 65.Xr random 4 66subsystem. 67.Sh SEE ALSO 68.Xr crypt 3 , 69.Xr crypto 4 , 70.Xr intro 4 , 71.Xr ipsec 4 , 72.Xr random 4 , 73.Xr crypto 7 , 74.Xr crypto 9 75.Sh HISTORY 76The 77.Nm 78driver first appeared in 79.Ox . 80The first 81.Fx 82release to include it was 83.Fx 6.0 . 84.Sh AUTHORS 85.An -nosplit 86The 87.Nm 88driver with AES encryption support was written by 89.An Jason Wright Aq Mt jason@OpenBSD.org . 90It was ported to 91.Fx 92and then extended to support SHA1 and SHA256 93by 94.An Pawel Jakub Dawidek Aq Mt pjd@FreeBSD.org . 95This manual page was written by 96.An Christian Brueffer Aq Mt brueffer@FreeBSD.org . 97