1.\"- 2.\" Copyright (c) 2014 Bjoern A. Zeeb 3.\" All rights reserved. 4.\" 5.\" This software was developed by SRI International and the University of 6.\" Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 7.\" ("MRC2"), as part of the DARPA MRC research programme. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28.\" SUCH DAMAGE. 29.\" 30.\" $FreeBSD$ 31.\" 32.Dd April 17, 2014 33.Dt NETFPGA10G_NF10BMAC 4 34.Os 35.Sh NAME 36.Nm netfpga10g_nf10bmac 37.Nd driver for the NetFPGA-10G Embedded CPU Ethernet Core 38.Sh SYNOPSIS 39.Cd "device netfpga10g_nf10bmac" 40.Sh DESCRIPTION 41The 42.Nm 43device driver provides support for the NetFPGA-10G Embedded CPU Ethernet 44Core. 45.Sh HARDWARE 46The current version of the 47.Nm 48driver works with one PIO mode interface of the 49NetFPGA-10G Embedded CPU Ethernet Core version 1.00a. 50.Sh SEE ALSO 51.Xr netintro 4 , 52.Xr ifconfig 8 53.Rs 54.%T NetFPGA-10G Wiki 55.%U https://github.com/NetFPGA/NetFPGA-public/wiki 56.Re 57.Sh HISTORY 58The 59.Nm 60device driver first appeared in 61.Fx 11.0 . 62.Sh AUTHORS 63This software and this manual page were 64developed by SRI International and the University of Cambridge Computer 65Laboratory under DARPA/AFRL contract 66.Pq FA8750-11-C-0249 67.Pq Do MRC2 Dc , 68as part of the DARPA MRC research programme. 69The device driver was written by 70.An Bjoern A. Zeeb . 71