1.\"- 2.\" Copyright (c) 2014 Bjoern A. Zeeb 3.\" All rights reserved. 4.\" 5.\" This software was developed by SRI International and the University of 6.\" Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 7.\" ("MRC2"), as part of the DARPA MRC research programme. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28.\" SUCH DAMAGE. 29.\" 30.Dd April 17, 2014 31.Dt NETFPGA10G_NF10BMAC 4 32.Os 33.Sh NAME 34.Nm netfpga10g_nf10bmac 35.Nd driver for the NetFPGA-10G Embedded CPU Ethernet Core 36.Sh SYNOPSIS 37.Cd "device netfpga10g_nf10bmac" 38.Sh DESCRIPTION 39The 40.Nm 41device driver provides support for the NetFPGA-10G Embedded CPU Ethernet 42Core. 43.Sh HARDWARE 44The current version of the 45.Nm 46driver works with one PIO mode interface of the 47NetFPGA-10G Embedded CPU Ethernet Core version 1.00a. 48.Sh SEE ALSO 49.Xr netintro 4 , 50.Xr ifconfig 8 51.Rs 52.%T NetFPGA-10G Wiki 53.%U https://github.com/NetFPGA/NetFPGA-public/wiki 54.Re 55.Sh HISTORY 56The 57.Nm 58device driver first appeared in 59.Fx 11.0 . 60.Sh AUTHORS 61This software and this manual page were 62developed by SRI International and the University of Cambridge Computer 63Laboratory under DARPA/AFRL contract 64.Pq FA8750-11-C-0249 65.Pq Do MRC2 Dc , 66as part of the DARPA MRC research programme. 67The device driver was written by 68.An Bjoern A. Zeeb . 69