xref: /freebsd/share/man/man4/mca.4 (revision 9c4a41d33b4620c46e2aa7d403ac49caf4b5d7b9)
1*9c4a41d3SJonathan T. Looney.\"
2*9c4a41d3SJonathan T. Looney.\" Copyright (c) 2026 The FreeBSD Project
3*9c4a41d3SJonathan T. Looney.\"
4*9c4a41d3SJonathan T. Looney.\" SPDX-License-Identifier: BSD-2-Clause
5*9c4a41d3SJonathan T. Looney.\"
6*9c4a41d3SJonathan T. Looney.Dd January 14, 2026
7*9c4a41d3SJonathan T. Looney.Dt MCA 4 amd64
8*9c4a41d3SJonathan T. Looney.Os
9*9c4a41d3SJonathan T. Looney.Sh NAME
10*9c4a41d3SJonathan T. Looney.Nm mca
11*9c4a41d3SJonathan T. Looney.Nd Machine Check Architecture
12*9c4a41d3SJonathan T. Looney.Sh DESCRIPTION
13*9c4a41d3SJonathan T. LooneyThe
14*9c4a41d3SJonathan T. Looney.Nm
15*9c4a41d3SJonathan T. Looneysubsystem provides support for the x86 Machine Check Architecture.
16*9c4a41d3SJonathan T. LooneyThe CPU uses this architecture to report various hardware problems,
17*9c4a41d3SJonathan T. Looneyranging from correctible errors to uncorrectible fatal errors.
18*9c4a41d3SJonathan T. LooneyThe
19*9c4a41d3SJonathan T. Looney.Nm
20*9c4a41d3SJonathan T. Looneysubsystem processes the errors reported by the CPU and logs them
21*9c4a41d3SJonathan T. Looneyaccording to the user-supplied configuration.
22*9c4a41d3SJonathan T. Looney.Pp
23*9c4a41d3SJonathan T. LooneyThe
24*9c4a41d3SJonathan T. Looney.Nm
25*9c4a41d3SJonathan T. Looneysubsystem is automatically compiled into every x86 kernel.
26*9c4a41d3SJonathan T. Looney.Sh LOGGING
27*9c4a41d3SJonathan T. LooneyBy default, every message is logged to four locations:
28*9c4a41d3SJonathan T. Looney.Bl -bullet
29*9c4a41d3SJonathan T. Looney.It
30*9c4a41d3SJonathan T. LooneyThe console
31*9c4a41d3SJonathan T. Looney.It
32*9c4a41d3SJonathan T. LooneyThe system log (using the
33*9c4a41d3SJonathan T. Looney.Dv LOG_KERN
34*9c4a41d3SJonathan T. Looney.Xr syslog 3
35*9c4a41d3SJonathan T. Looneyfacility)
36*9c4a41d3SJonathan T. Looney.It
37*9c4a41d3SJonathan T. LooneyAn in-kernel cache of event records
38*9c4a41d3SJonathan T. Looney.It
39*9c4a41d3SJonathan T. LooneyA statistics array
40*9c4a41d3SJonathan T. Looney.El
41*9c4a41d3SJonathan T. Looney.Pp
42*9c4a41d3SJonathan T. LooneyAn administrator can disable console logging of non-fatal errors using the
43*9c4a41d3SJonathan T. Looney.Va hw.mca.uselog
44*9c4a41d3SJonathan T. Looney.Xr sysctl 8
45*9c4a41d3SJonathan T. Looneyor tunable setting.
46*9c4a41d3SJonathan T. LooneyFatal errors are always logged to the console.
47*9c4a41d3SJonathan T. Looney.Pp
48*9c4a41d3SJonathan T. LooneyThe in-kernel cache of event records can be accessed from userspace using the
49*9c4a41d3SJonathan T. Looney.Va hw.mca.records
50*9c4a41d3SJonathan T. Looney.Xr sysctl 8
51*9c4a41d3SJonathan T. Looneynode.
52*9c4a41d3SJonathan T. LooneyBy default, the in-kernel cache of event records grows without bound and
53*9c4a41d3SJonathan T. Looneycontains records for all
54*9c4a41d3SJonathan T. Looney.Nm
55*9c4a41d3SJonathan T. Looneyevents received since system boot.
56*9c4a41d3SJonathan T. LooneyThe cache can be limited (in which case it turns into a ring buffer) or
57*9c4a41d3SJonathan T. Looneydisabled altogether using the
58*9c4a41d3SJonathan T. Looney.Va hw.mca.maxcount
59*9c4a41d3SJonathan T. Looney.Xr sysctl 8
60*9c4a41d3SJonathan T. Looneyor tunable setting.
61*9c4a41d3SJonathan T. Looney.Pp
62*9c4a41d3SJonathan T. LooneyThe statistics array can be retrieved using the
63*9c4a41d3SJonathan T. Looney.Va hw.mca.stats
64*9c4a41d3SJonathan T. Looney.Xr sysctl 8
65*9c4a41d3SJonathan T. Looneynode.
66*9c4a41d3SJonathan T. Looney.Sh SYSCTL VARIABLES
67*9c4a41d3SJonathan T. LooneyThe subsystem has a number of configuration options to control the
68*9c4a41d3SJonathan T. Looneyway events are processed and logged.
69*9c4a41d3SJonathan T. LooneyThese options are configured via
70*9c4a41d3SJonathan T. Looney.Xr sysctl 8
71*9c4a41d3SJonathan T. Looneyvariables or tunables.
72*9c4a41d3SJonathan T. LooneyThese settings control things such as log destination, event limiting,
73*9c4a41d3SJonathan T. Looneyand sampling.
74*9c4a41d3SJonathan T. LooneyThese settings directly impact both the completeness of logs and the performance
75*9c4a41d3SJonathan T. Looneyimpact of processing
76*9c4a41d3SJonathan T. Looney.Nm
77*9c4a41d3SJonathan T. Looneyevents.
78*9c4a41d3SJonathan T. LooneyA system administrator may want to review these and modify them to obtain
79*9c4a41d3SJonathan T. Looneythe appropriate behavior in their environment.
80*9c4a41d3SJonathan T. Looney.Bl -tag -width indent
81*9c4a41d3SJonathan T. Looney.It Va hw.mca.enabled
82*9c4a41d3SJonathan T. Looney(Only settable as a tunable.)
83*9c4a41d3SJonathan T. Looney.Pp
84*9c4a41d3SJonathan T. LooneyIf set to 0, the CPU is not configured to send
85*9c4a41d3SJonathan T. Looney.Nm
86*9c4a41d3SJonathan T. Looneymessages to the kernel.
87*9c4a41d3SJonathan T. Looney.Pp
88*9c4a41d3SJonathan T. LooneyDefault is 1 (enabled).
89*9c4a41d3SJonathan T. Looney.It Va hw.mca.log_corrected
90*9c4a41d3SJonathan T. Looney(Settable as a tunable or sysctl.)
91*9c4a41d3SJonathan T. Looney.Pp
92*9c4a41d3SJonathan T. LooneyIf enabled, corrected messages are logged to console, syslog, the in-kernel
93*9c4a41d3SJonathan T. Looneyevent cache, and the statistics array (subject to separate configuration
94*9c4a41d3SJonathan T. Looneycontrolling those facilities).
95*9c4a41d3SJonathan T. LooneyIf disabled, corrected messages are only logged to the in-kernel event
96*9c4a41d3SJonathan T. Looneycache (subject to separate configuration controlling that facility).
97*9c4a41d3SJonathan T. Looney.Pp
98*9c4a41d3SJonathan T. LooneyDefault is 1 (enabled).
99*9c4a41d3SJonathan T. Looney.It Va hw.mca.intel6h_HSD131
100*9c4a41d3SJonathan T. Looney(Only settable as a tunable.)
101*9c4a41d3SJonathan T. Looney.Pp
102*9c4a41d3SJonathan T. LooneyThis setting enables a workaround for benign corrected parity errors which
103*9c4a41d3SJonathan T. Looneymay be reported by certain Intel desktop Haswell CPUs.
104*9c4a41d3SJonathan T. Looney(The name "HSD131" comes from the name of the Intel erratum report about this
105*9c4a41d3SJonathan T. Looneyissue.)
106*9c4a41d3SJonathan T. Looney.Pp
107*9c4a41d3SJonathan T. LooneyDefault is 0 (disabled).
108*9c4a41d3SJonathan T. Looney.It Va hw.mca.amd10h_L1TP
109*9c4a41d3SJonathan T. Looney(Only settable as a tunable.)
110*9c4a41d3SJonathan T. Looney.Pp
111*9c4a41d3SJonathan T. LooneyEnable logging of level one TLB parity errors on certain AMD CPUs.
112*9c4a41d3SJonathan T. LooneyThis option has no impact on other CPUs.
113*9c4a41d3SJonathan T. Looney.Pp
114*9c4a41d3SJonathan T. LooneyDefault is 1 (enabled).
115*9c4a41d3SJonathan T. Looney.It Va hw.mca.erratum383
116*9c4a41d3SJonathan T. Looney(Only settable as a tunable.)
117*9c4a41d3SJonathan T. Looney.Pp
118*9c4a41d3SJonathan T. LooneyThis setting enables a workaround for Erratum 383 on AMD Family 10h CPUs.
119*9c4a41d3SJonathan T. LooneyThe erratum changes the way pages are promoted to or demoted from being
120*9c4a41d3SJonathan T. Looneysuper-pages.
121*9c4a41d3SJonathan T. LooneyOn affected AMD CPUs, either
122*9c4a41d3SJonathan T. Looney.Va hw.mca.amd10h_L1TP
123*9c4a41d3SJonathan T. Looneyor
124*9c4a41d3SJonathan T. Looney.Va hw.mca.erratum383
125*9c4a41d3SJonathan T. Looneymust be on.
126*9c4a41d3SJonathan T. LooneyIf both are off, the system will dynamically enable
127*9c4a41d3SJonathan T. Looney.Va hw.mca.erratum383
128*9c4a41d3SJonathan T. Looneyat boot time.
129*9c4a41d3SJonathan T. Looney.Pp
130*9c4a41d3SJonathan T. LooneyDefault is 0 (disabled).
131*9c4a41d3SJonathan T. Looney.It Va hw.mca.uselog
132*9c4a41d3SJonathan T. Looney(Settable as a tunable or sysctl.)
133*9c4a41d3SJonathan T. Looney.Pp
134*9c4a41d3SJonathan T. LooneyIf enabled, the system will send messages about non-fatal
135*9c4a41d3SJonathan T. Looney.Nm
136*9c4a41d3SJonathan T. Looneyevents to syslog and not to the console.
137*9c4a41d3SJonathan T. LooneyIf disabled, the system will send messages about non-fatal
138*9c4a41d3SJonathan T. Looney.Nm
139*9c4a41d3SJonathan T. Looneyevents to both syslog and the console.
140*9c4a41d3SJonathan T. LooneyFatal events are always logged to the console.
141*9c4a41d3SJonathan T. Looney.Pp
142*9c4a41d3SJonathan T. LooneyDefault is false (disabled).
143*9c4a41d3SJonathan T. Looney.It Va hw.mca.stats
144*9c4a41d3SJonathan T. Looney(Read-only sysctl.)
145*9c4a41d3SJonathan T. Looney.Pp
146*9c4a41d3SJonathan T. LooneyThis returns an array of
147*9c4a41d3SJonathan T. Looney.Va MCA_T_COUNT
148*9c4a41d3SJonathan T. Looneyuint64_t values.
149*9c4a41d3SJonathan T. LooneyThe
150*9c4a41d3SJonathan T. Looney.Vt "enum mca_stat_types"
151*9c4a41d3SJonathan T. Looneydefinition in
152*9c4a41d3SJonathan T. Looney.In x86/mca.h
153*9c4a41d3SJonathan T. Looneyprovides the value of
154*9c4a41d3SJonathan T. Looney.Va MCA_T_COUNT
155*9c4a41d3SJonathan T. Looneyand the index values for various event types.
156*9c4a41d3SJonathan T. Looney.It Va hw.mca.log_interval
157*9c4a41d3SJonathan T. Looney(Settable as a tunable or sysctl.)
158*9c4a41d3SJonathan T. Looney.Pp
159*9c4a41d3SJonathan T. LooneyThis sets the minimum time (in seconds) between logging correctible errors.
160*9c4a41d3SJonathan T. LooneyThe rate limit is only applied after the system records a reasonable
161*9c4a41d3SJonathan T. Looneynumber of errors of the same type.
162*9c4a41d3SJonathan T. LooneyThe goal is to reduce the impact of the system seeing and attempting to log
163*9c4a41d3SJonathan T. Looneya burst of similar errors, which can be expensive (especially when printed
164*9c4a41d3SJonathan T. Looneyto the console).
165*9c4a41d3SJonathan T. LooneyIf this setting is 0, no rate limit is applied.
166*9c4a41d3SJonathan T. Looney.Pp
167*9c4a41d3SJonathan T. LooneyDefault is 0 (no rate limit).
168*9c4a41d3SJonathan T. Looney.It Va hw.mca.cmc_throttle
169*9c4a41d3SJonathan T. Looney(Settable as a tunable or sysctl. Only available if
170*9c4a41d3SJonathan T. Looney.Xr apic 4
171*9c4a41d3SJonathan T. Looneysupport is enabled and the hardware supports CMC interrupt throttling.)
172*9c4a41d3SJonathan T. Looney.Pp
173*9c4a41d3SJonathan T. LooneyThis sets the maximum time (in seconds) to throttle CMC interrupts.
174*9c4a41d3SJonathan T. LooneyIn normal operation, the system attempts to receive CMC interrupts as soon as
175*9c4a41d3SJonathan T. Looneyan event occurs.
176*9c4a41d3SJonathan T. LooneyHowever, if a high rate of events occurs in a short time, the system will
177*9c4a41d3SJonathan T. Looneybegin throttling the CMC interrupts.
178*9c4a41d3SJonathan T. LooneyWhile the events continue to occur at a high rate, the system will gradually
179*9c4a41d3SJonathan T. Looneyincrease the throttling interval until it reaches the
180*9c4a41d3SJonathan T. Looney.Va hw.mca.cmc_throttle
181*9c4a41d3SJonathan T. Looneysetting.
182*9c4a41d3SJonathan T. Looney.Pp
183*9c4a41d3SJonathan T. LooneyDefault is 60 seconds.
184*9c4a41d3SJonathan T. Looney.It Va hw.mca.count
185*9c4a41d3SJonathan T. Looney(Read-only sysctl.)
186*9c4a41d3SJonathan T. Looney.Pp
187*9c4a41d3SJonathan T. LooneyThis returns the current number of
188*9c4a41d3SJonathan T. Looney.Nm
189*9c4a41d3SJonathan T. Looneyrecords in the in-kernel cache.
190*9c4a41d3SJonathan T. LooneyThis can be used to determine how many records are available to read with the
191*9c4a41d3SJonathan T. Looney.Va hw.mca.records
192*9c4a41d3SJonathan T. Looney.Xr sysctl 8
193*9c4a41d3SJonathan T. Looneyinterface.
194*9c4a41d3SJonathan T. LooneyIt can also be used to monitor the amount of memory used by the in-kernel
195*9c4a41d3SJonathan T. Looneyrecord cache.
196*9c4a41d3SJonathan T. Looney.It Va hw.mca.maxcount
197*9c4a41d3SJonathan T. Looney(Settable as a tunable or sysctl.)
198*9c4a41d3SJonathan T. Looney.Pp
199*9c4a41d3SJonathan T. LooneyThis setting controls the size and behavior of the in-kernel cache of
200*9c4a41d3SJonathan T. Looney.Nm
201*9c4a41d3SJonathan T. Looneyrecords.
202*9c4a41d3SJonathan T. LooneyIf the setting is -1, the in-kernel cache grows without bounds and contains a
203*9c4a41d3SJonathan T. Looneycomplete record events since boot or the last time the
204*9c4a41d3SJonathan T. Looney.Va hw.mca.maxcount
205*9c4a41d3SJonathan T. Looneysetting was changed.
206*9c4a41d3SJonathan T. LooneyIf the setting is 0, the in-kernel cache is disabled.
207*9c4a41d3SJonathan T. LooneyIf the setting is a positive integer, the in-kernel cache functions as a ring
208*9c4a41d3SJonathan T. Looneybuffer with the number of entries defined by the setting.
209*9c4a41d3SJonathan T. Looney.Pp
210*9c4a41d3SJonathan T. LooneyDefault is -1 (unlimited).
211*9c4a41d3SJonathan T. Looney.It Va hw.mca.interval
212*9c4a41d3SJonathan T. Looney(Settable as a tunable or sysctl.)
213*9c4a41d3SJonathan T. Looney.Pp
214*9c4a41d3SJonathan T. LooneyThis setting controls how often (in seconds) the kernel should proactively
215*9c4a41d3SJonathan T. Looneyscan for new
216*9c4a41d3SJonathan T. Looney.Nm
217*9c4a41d3SJonathan T. Looneyevents.
218*9c4a41d3SJonathan T. LooneyIn many circumstances, the CPU will send an interrupt to signal new events.
219*9c4a41d3SJonathan T. LooneyHowever, there are cases where the periodic scan for events will discover
220*9c4a41d3SJonathan T. Looneynew events.
221*9c4a41d3SJonathan T. Looney.Pp
222*9c4a41d3SJonathan T. LooneyDefault is 300 seconds.
223*9c4a41d3SJonathan T. Looney.It Va hw.mca.force_scan
224*9c4a41d3SJonathan T. Looney(Settable only as a sysctl.)
225*9c4a41d3SJonathan T. Looney.Pp
226*9c4a41d3SJonathan T. LooneySetting this to any non-zero value will force an immediate scan for
227*9c4a41d3SJonathan T. Looney.Nm
228*9c4a41d3SJonathan T. Looneyevents.
229*9c4a41d3SJonathan T. LooneySetting this to zero has no effect.
230*9c4a41d3SJonathan T. LooneyThis is functionally a write-only setting.
231*9c4a41d3SJonathan T. LooneyThe current value is always 0, even when a scan is running.
232*9c4a41d3SJonathan T. Looney.Pp
233*9c4a41d3SJonathan T. LooneyDefault is 0 (no scan requested).
234*9c4a41d3SJonathan T. Looney.It Va hw.mca.records.n
235*9c4a41d3SJonathan T. Looney(Read-only sysctl.)
236*9c4a41d3SJonathan T. Looney.Pp
237*9c4a41d3SJonathan T. LooneyThis is used to copy
238*9c4a41d3SJonathan T. Looney.Nm
239*9c4a41d3SJonathan T. Looneyrecords from the in-kernel cache to a user space process.
240*9c4a41d3SJonathan T. LooneyThe
241*9c4a41d3SJonathan T. Looney.Va n
242*9c4a41d3SJonathan T. Looneyvalue in the
243*9c4a41d3SJonathan T. Looney.Xr sysctl 8
244*9c4a41d3SJonathan T. Looneynode is an integer index into the in-kernel cache.
245*9c4a41d3SJonathan T. Looney(Or, put differently, the "new" value describes how many records the kernel
246*9c4a41d3SJonathan T. Looneyshould skip to find the desired record.)
247*9c4a41d3SJonathan T. LooneyThe return value is a
248*9c4a41d3SJonathan T. Looney.Vt "struct mca_record" ,
249*9c4a41d3SJonathan T. Looneywhich is defined in
250*9c4a41d3SJonathan T. Looney.In x86/mca.h .
251*9c4a41d3SJonathan T. Looney.El
252*9c4a41d3SJonathan T. Looney.Sh LOADER TUNABLES
253*9c4a41d3SJonathan T. LooneyTunables can be set at the
254*9c4a41d3SJonathan T. Looney.Xr loader 8
255*9c4a41d3SJonathan T. Looneyprompt before booting the kernel or stored in
256*9c4a41d3SJonathan T. Looney.Pa /boot/loader.conf .
257*9c4a41d3SJonathan T. LooneyThe tunables all have corresponding
258*9c4a41d3SJonathan T. Looney.Xr sysctl 8
259*9c4a41d3SJonathan T. Looneyentries.
260*9c4a41d3SJonathan T. LooneyThe tunables are listed above in the
261*9c4a41d3SJonathan T. Looney.Sx SYSCTL VARIABLES
262*9c4a41d3SJonathan T. Looneysection.
263*9c4a41d3SJonathan T. Looney.Sh COMPATIBILITY
264*9c4a41d3SJonathan T. Looney.Nm
265*9c4a41d3SJonathan T. Looneyis only available on x86 systems.
266*9c4a41d3SJonathan T. Looney.Sh SEE ALSO
267*9c4a41d3SJonathan T. Looney.Xr loader.conf 5 ,
268*9c4a41d3SJonathan T. Looney.Xr sysctl 8 ,
269*9c4a41d3SJonathan T. Looney.Xr syslogd 8
270*9c4a41d3SJonathan T. Looney.Sh AUTHORS
271*9c4a41d3SJonathan T. LooneyThe
272*9c4a41d3SJonathan T. Looney.Nm
273*9c4a41d3SJonathan T. Looneysubsystem was originally written by
274*9c4a41d3SJonathan T. Looney.An John Baldwin Aq Mt jhb@FreeBSD.org .
275*9c4a41d3SJonathan T. Looney.Pp
276*9c4a41d3SJonathan T. LooneyThis manual page was written by
277*9c4a41d3SJonathan T. Looney.An Jonathan Looney Aq Mt jtl@FreeBSD.org .
278