1.\" 2.\" Copyright (c) 2013 Thomas Skibo 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. The name of the author may not be used to endorse or promote products 11.\" derived from this software without specific prior written permission. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd February 28, 2013 28.Dt DEVCFG 4 29.Os 30.Sh NAME 31.Nm devcfg 32.Nd Zynq PL device config interface 33.Sh SYNOPSIS 34.Cd device devcfg 35.Sh DESCRIPTION 36The special file 37.Pa /dev/devcfg 38can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000. 39.Pp 40On the first write to the character device at file offset 0, the 41.Nm 42driver 43asserts the top-level PL reset signals, disables the PS-PL level shifters, 44and clears the PL configuration. 45Write data is sent to the PCAP (processor configuration access port). 46When the PL asserts the DONE signal, the devcfg driver will enable the level 47shifters and release the top-level PL reset signals. 48.Pp 49The PL (FPGA) can be configured by writing the bitstream to the character 50device like this: 51.Bd -literal -offset indent 52cat design.bit.bin > /dev/devcfg 53.Ed 54.Pp 55The file should not be confused with the .bit file output by the FPGA 56design tools. 57It is the binary form of the configuration bitstream. 58The Xilinx 59.Ic promgen 60tool can do the conversion: 61.Bd -literal -offset indent 62promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin 63.Ed 64.Sh SYSCTL VARIABLES 65The 66.Nm 67driver provides the following 68.Xr sysctl 8 69variables: 70.Bl -tag -width 4n 71.It Va hw.fpga.pl_done 72.Pp 73This variable always reflects the status of the PL's DONE signal. 74A 1 means the PL section has been properly programmed. 75.It Va hw.fpga.en_level_shifters 76.Pp 77This variable controls if the PS-PL level shifters are enabled after the 78PL section has been reconfigured. 79This variable is 1 by default but setting it to 0 allows the PL section to be 80programmed with configurations that do not interface to the PS section of the 81part. 82Changing this value has no effect on the level shifters until the next device 83reconfiguration. 84.El 85.Sh FILES 86.Bl -tag -width 12n 87.It Pa /dev/devcfg 88Character device for the 89.Nm 90driver. 91.El 92.Sh SEE ALSO 93Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585) 94.Sh AUTHORS 95.An Thomas Skibo 96