1.\" 2.\" Copyright (c) 2013 Thomas Skibo 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. The name of the author may not be used to endorse or promote products 11.\" derived from this software without specific prior written permission. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd February 28, 2013 26.Dt DEVCFG 4 27.Os 28.Sh NAME 29.Nm devcfg 30.Nd Zynq PL device config interface 31.Sh SYNOPSIS 32.Cd device devcfg 33.Sh DESCRIPTION 34The special file 35.Pa /dev/devcfg 36can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000. 37.Pp 38On the first write to the character device at file offset 0, the 39.Nm 40driver 41asserts the top-level PL reset signals, disables the PS-PL level shifters, 42and clears the PL configuration. 43Write data is sent to the PCAP (processor configuration access port). 44When the PL asserts the DONE signal, the devcfg driver will enable the level 45shifters and release the top-level PL reset signals. 46.Pp 47The PL (FPGA) can be configured by writing the bitstream to the character 48device like this: 49.Bd -literal -offset indent 50cat design.bit.bin > /dev/devcfg 51.Ed 52.Pp 53The file should not be confused with the .bit file output by the FPGA 54design tools. 55It is the binary form of the configuration bitstream. 56The Xilinx 57.Ic promgen 58tool can do the conversion: 59.Bd -literal -offset indent 60promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin 61.Ed 62.Sh SYSCTL VARIABLES 63The 64.Nm 65driver provides the following 66.Xr sysctl 8 67variables: 68.Bl -tag -width 4n 69.It Va hw.fpga.pl_done 70.Pp 71This variable always reflects the status of the PL's DONE signal. 72A 1 means the PL section has been properly programmed. 73.It Va hw.fpga.en_level_shifters 74.Pp 75This variable controls if the PS-PL level shifters are enabled after the 76PL section has been reconfigured. 77This variable is 1 by default but setting it to 0 allows the PL section to be 78programmed with configurations that do not interface to the PS section of the 79part. 80Changing this value has no effect on the level shifters until the next device 81reconfiguration. 82.El 83.Sh FILES 84.Bl -tag -width 12n 85.It Pa /dev/devcfg 86Character device for the 87.Nm 88driver. 89.El 90.Sh SEE ALSO 91Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585) 92.Sh AUTHORS 93.An Thomas Skibo 94