1.\" Copyright (c) 2015 EMC / Isilon Storage Division 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd August 24, 2015 28.Dt IOAT 4 29.Os 30.Sh NAME 31.Nm I/OAT 32.Nd Intel I/O Acceleration Technology 33.Sh SYNOPSIS 34.Cd "device ioat" 35In 36.Xr loader.conf 5 : 37.Pp 38.Cd hw.ioat.force_legacy_interrupts=0 39.Pp 40In 41.Xr loader.conf 5 or 42.Xr sysctl.conf 5 : 43.Pp 44.Cd hw.ioat.enable_ioat_test=0 45.Cd hw.ioat.debug_level=0 46(only critical errors; maximum of 3) 47.Pp 48.Ft typedef void 49.Fn (*bus_dmaengine_callback_t) "void *arg" 50.Pp 51.Ft bus_dmaengine_t 52.Fn ioat_get_dmaengine "uint32_t channel_index" 53.Ft void 54.Fn ioat_acquire "bus_dmaengine_t dmaengine" 55.Ft void 56.Fn ioat_release "bus_dmaengine_t dmaengine" 57.Ft struct bus_dmadesc * 58.Fo ioat_copy 59.Fa "bus_dmaengine_t dmaengine" 60.Fa "bus_addr_t dst" 61.Fa "bus_addr_t src" 62.Fa "bus_size_t len" 63.Fa "bus_dmaengine_callback_t callback_fn" 64.Fa "void *callback_arg" 65.Fa "uint32_t flags" 66.Fc 67.Ft struct bus_dmadesc * 68.Fo ioat_null 69.Fa "bus_dmaengine_t dmaengine" 70.Fa "bus_dmaengine_callback_t callback_fn" 71.Fa "void *callback_arg" 72.Fa "uint32_t flags" 73.Fc 74.Sh DESCRIPTION 75The 76.Nm 77driver provides a kernel API to a variety of DMA engines on some Intel server 78platforms. 79.Pp 80There is a number of DMA channels per CPU package. 81(Typically 4 or 8.) 82Each may be used independently. 83Operations on a single channel proceed sequentially. 84.Pp 85Copy operations may be used to offload memory copies to the DMA engines. 86.Pp 87Null operations do nothing, but may be used to test the interrupt and callback 88mechanism. 89.Pp 90All operations can optionally trigger an interrupt at completion with the 91.Ar DMA_EN_INT 92flag. 93For example, a user might submit multiple operations to the same channel and 94only enable an interrupt and callback for the last operation. 95.Sh USAGE 96A typical user will lookup the DMA engine object for a given channel with 97.Fn ioat_get_dmaengine . 98When the user wants to offload a copy, they will first 99.Fn ioat_acquire 100the 101.Ar bus_dmaengine_t 102object for exclusive access to enqueue operations on that channel. 103Then, they will submit one or more operations using 104.Fn ioat_copy 105or 106.Fn ioat_null . 107Finally, they will 108.Fn ioat_release 109the 110.Ar bus_dmaengine_t 111to drop their exclusive access to the channel. 112The routine they provided for the 113.Fa callback_fn 114argument will be invoked with the provided 115.Fa callback_arg 116when the operation is complete. 117.Pp 118For an example of usage, see 119.Pa src/sys/dev/ioat/ioat_test.c . 120.Sh FILES 121.Bl -tag -compat 122.It Pa /dev/ioat_test 123test device for 124.Xr ioatcontrol 8 125.El 126.Sh SEE ALSO 127.Xr ioatcontrol 8 128.Sh HISTORY 129The 130.Nm 131driver first appeared in 132.Fx 11.0 . 133.Sh AUTHORS 134The 135.Nm 136driver was developed by 137.An \&Jim Harris Aq Mt jimharris@FreeBSD.org , 138and 139.An \&Carl Delsey Aq Mt carl.r.delsey@intel.com . 140This manual page was written by 141.An \&Conrad Meyer Aq Mt cem@FreeBSD.org . 142.Sh CAVEATS 143Copy operation takes bus addresses as parameters, not virtual addresses. 144.Pp 145Copies larger than max transfer size (1MB) are not supported. 146Future versions will likely support this by breaking up the transfer into 147smaller sizes. 148.Sh BUGS 149The 150.Nm 151driver only supports copy and null operations at this time. 152The driver does not yet support advanced DMA modes, such as XOR, that some 153I/OAT devices support. 154