1.\" Copyright (c) 2015 EMC / Isilon Storage Division 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd January 7, 2016 28.Dt IOAT 4 29.Os 30.Sh NAME 31.Nm I/OAT 32.Nd Intel I/O Acceleration Technology 33.Sh SYNOPSIS 34To compile this driver into your kernel, 35place the following line in your kernel configuration file: 36.Bd -ragged -offset indent 37.Cd "device ioat" 38.Ed 39.Pp 40Or, to load the driver as a module at boot, place the following line in 41.Xr loader.conf 5 : 42.Bd -literal -offset indent 43ioat_load="YES" 44.Ed 45.Pp 46In 47.Xr loader.conf 5 : 48.Pp 49.Cd hw.ioat.force_legacy_interrupts=0 50.Pp 51In 52.Xr loader.conf 5 or 53.Xr sysctl.conf 5 : 54.Pp 55.Cd hw.ioat.enable_ioat_test=0 56.Cd hw.ioat.debug_level=0 57(only critical errors; maximum of 3) 58.Pp 59.Ft typedef void 60.Fn (*bus_dmaengine_callback_t) "void *arg" "int error" 61.Pp 62.Ft bus_dmaengine_t 63.Fn ioat_get_dmaengine "uint32_t channel_index" 64.Ft void 65.Fn ioat_put_dmaengine "bus_dmaengine_t dmaengine" 66.Ft int 67.Fn ioat_get_hwversion "bus_dmaengine_t dmaengine" 68.Ft size_t 69.Fn ioat_get_max_io_size "bus_dmaengine_t dmaengine" 70.Ft int 71.Fn ioat_set_interrupt_coalesce "bus_dmaengine_t dmaengine" "uint16_t delay" 72.Ft uint16_t 73.Fn ioat_get_max_coalesce_period "bus_dmaengine_t dmaengine" 74.Ft void 75.Fn ioat_acquire "bus_dmaengine_t dmaengine" 76.Ft int 77.Fn ioat_acquire_reserve "bus_dmaengine_t dmaengine" "uint32_t n" "int mflags" 78.Ft void 79.Fn ioat_release "bus_dmaengine_t dmaengine" 80.Ft struct bus_dmadesc * 81.Fo ioat_copy 82.Fa "bus_dmaengine_t dmaengine" 83.Fa "bus_addr_t dst" 84.Fa "bus_addr_t src" 85.Fa "bus_size_t len" 86.Fa "bus_dmaengine_callback_t callback_fn" 87.Fa "void *callback_arg" 88.Fa "uint32_t flags" 89.Fc 90.Ft struct bus_dmadesc * 91.Fo ioat_copy_8k_aligned 92.Fa "bus_dmaengine_t dmaengine" 93.Fa "bus_addr_t dst1" 94.Fa "bus_addr_t dst2" 95.Fa "bus_addr_t src1" 96.Fa "bus_addr_t src2" 97.Fa "bus_dmaengine_callback_t callback_fn" 98.Fa "void *callback_arg" 99.Fa "uint32_t flags" 100.Fc 101.Ft struct bus_dmadesc * 102.Fo ioat_blockfill 103.Fa "bus_dmaengine_t dmaengine" 104.Fa "bus_addr_t dst" 105.Fa "uint64_t fillpattern" 106.Fa "bus_size_t len" 107.Fa "bus_dmaengine_callback_t callback_fn" 108.Fa "void *callback_arg" 109.Fa "uint32_t flags" 110.Fc 111.Ft struct bus_dmadesc * 112.Fo ioat_null 113.Fa "bus_dmaengine_t dmaengine" 114.Fa "bus_dmaengine_callback_t callback_fn" 115.Fa "void *callback_arg" 116.Fa "uint32_t flags" 117.Fc 118.Sh DESCRIPTION 119The 120.Nm 121driver provides a kernel API to a variety of DMA engines on some Intel server 122platforms. 123.Pp 124There is a number of DMA channels per CPU package. 125(Typically 4 or 8.) 126Each may be used independently. 127Operations on a single channel proceed sequentially. 128.Pp 129Blockfill operations can be used to write a 64-bit pattern to memory. 130.Pp 131Copy operations can be used to offload memory copies to the DMA engines. 132.Pp 133Null operations do nothing, but may be used to test the interrupt and callback 134mechanism. 135.Pp 136All operations can optionally trigger an interrupt at completion with the 137.Ar DMA_EN_INT 138flag. 139For example, a user might submit multiple operations to the same channel and 140only enable an interrupt and callback for the last operation. 141.Pp 142The hardware can delay and coalesce interrupts on a given channel for a 143configurable period of time, in microseconds. 144This may be desired to reduce the processing and interrupt overhead per 145descriptor, especially for workflows consisting of many small operations. 146Software can control this on a per-channel basis with the 147.Fn ioat_set_interrupt_coalesce 148API. 149The 150.Fn ioat_get_max_coalesce_period 151API can be used to determine the maximum coalescing period supported by the 152hardware, in microseconds. 153Current platforms support up to a 16.383 millisecond coalescing period. 154Optimal configuration will vary by workflow and desired operation latency. 155.Pp 156All operations are safe to use in a non-blocking context with the 157.Ar DMA_NO_WAIT 158flag. 159(Of course, allocations may fail and operations requested with 160.Ar DMA_NO_WAIT 161may return NULL.) 162.Pp 163All operations, as well as 164.Fn ioat_get_dmaengine , 165can return NULL in special circumstances. 166For example, if the 167.Nm 168driver is being unloaded, or the administrator has induced a hardware reset, or 169a usage error has resulted in a hardware error state that needs to be recovered 170from. 171.Pp 172It is invalid to attempt to submit new DMA operations in a 173.Fa bus_dmaengine_callback_t 174context. 175.Sh USAGE 176A typical user will lookup the DMA engine object for a given channel with 177.Fn ioat_get_dmaengine . 178When the user wants to offload a copy, they will first 179.Fn ioat_acquire 180the 181.Ar bus_dmaengine_t 182object for exclusive access to enqueue operations on that channel. 183Optionally, the user can reserve space by using 184.Fn ioat_acquire_reserve 185instead. 186If 187.Fn ioat_acquire_reserve 188succeeds, there is guaranteed to be room for 189.Fa N 190new operations in the internal ring buffer. 191Then, they will submit one or more operations using 192.Fn ioat_blockfill , 193.Fn ioat_copy , 194or 195.Fn ioat_null . 196After queuing one or more individual DMA operations, they will 197.Fn ioat_release 198the 199.Ar bus_dmaengine_t 200to drop their exclusive access to the channel. 201The routine they provided for the 202.Fa callback_fn 203argument will be invoked with the provided 204.Fa callback_arg 205when the operation is complete. 206When they are finished with the 207.Ar bus_dmaengine_t , 208the user should 209.Fn ioat_put_dmaengine . 210.Pp 211Users MUST NOT block between 212.Fn ioat_acquire 213and 214.Fn ioat_release . 215Users SHOULD NOT hold 216.Ar bus_dmaengine_t 217references for a very long time to enable fault recovery and kernel module 218unload. 219.Pp 220For an example of usage, see 221.Pa src/sys/dev/ioat/ioat_test.c . 222.Sh FILES 223.Bl -tag 224.It Pa /dev/ioat_test 225test device for 226.Xr ioatcontrol 8 227.El 228.Sh SEE ALSO 229.Xr ioatcontrol 8 230.Sh HISTORY 231The 232.Nm 233driver first appeared in 234.Fx 11.0 . 235.Sh AUTHORS 236The 237.Nm 238driver was developed by 239.An \&Jim Harris Aq Mt jimharris@FreeBSD.org , 240.An \&Carl Delsey Aq Mt carl.r.delsey@intel.com , 241and 242.An \&Conrad Meyer Aq Mt cem@FreeBSD.org . 243This manual page was written by 244.An \&Conrad Meyer Aq Mt cem@FreeBSD.org . 245.Sh CAVEATS 246Copy operation takes bus addresses as parameters, not virtual addresses. 247.Pp 248Buffers for individual copy operations must be physically contiguous. 249.Pp 250Copies larger than max transfer size (1MB, but may vary by hardware) are not 251supported. 252Future versions will likely support this by breaking up the transfer into 253smaller sizes. 254.Sh BUGS 255The 256.Nm 257driver only supports blockfill, copy, and null operations at this time. 258The driver does not yet support advanced DMA modes, such as XOR, that some 259I/OAT devices support. 260