1.\" Copyright (c) 2015 EMC / Isilon Storage Division 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd January 5, 2016 28.Dt IOAT 4 29.Os 30.Sh NAME 31.Nm I/OAT 32.Nd Intel I/O Acceleration Technology 33.Sh SYNOPSIS 34To compile this driver into your kernel, 35place the following line in your kernel configuration file: 36.Bd -ragged -offset indent 37.Cd "device ioat" 38.Ed 39.Pp 40Or, to load the driver as a module at boot, place the following line in 41.Xr loader.conf 5 : 42.Bd -literal -offset indent 43ioat_load="YES" 44.Ed 45.Pp 46In 47.Xr loader.conf 5 : 48.Pp 49.Cd hw.ioat.force_legacy_interrupts=0 50.Pp 51In 52.Xr loader.conf 5 or 53.Xr sysctl.conf 5 : 54.Pp 55.Cd hw.ioat.enable_ioat_test=0 56.Cd hw.ioat.debug_level=0 57(only critical errors; maximum of 3) 58.Pp 59.Ft typedef void 60.Fn (*bus_dmaengine_callback_t) "void *arg" "int error" 61.Pp 62.Ft bus_dmaengine_t 63.Fn ioat_get_dmaengine "uint32_t channel_index" 64.Ft void 65.Fn ioat_put_dmaengine "bus_dmaengine_t dmaengine" 66.Ft int 67.Fn ioat_get_hwversion "bus_dmaengine_t dmaengine" 68.Ft size_t 69.Fn ioat_get_max_io_size "bus_dmaengine_t dmaengine" 70.Ft int 71.Fn ioat_set_interrupt_coalesce "bus_dmaengine_t dmaengine" "uint16_t delay" 72.Ft uint16_t 73.Fn ioat_get_max_coalesce_period "bus_dmaengine_t dmaengine" 74.Ft void 75.Fn ioat_acquire "bus_dmaengine_t dmaengine" 76.Ft void 77.Fn ioat_release "bus_dmaengine_t dmaengine" 78.Ft struct bus_dmadesc * 79.Fo ioat_copy 80.Fa "bus_dmaengine_t dmaengine" 81.Fa "bus_addr_t dst" 82.Fa "bus_addr_t src" 83.Fa "bus_size_t len" 84.Fa "bus_dmaengine_callback_t callback_fn" 85.Fa "void *callback_arg" 86.Fa "uint32_t flags" 87.Fc 88.Ft struct bus_dmadesc * 89.Fo ioat_copy_8k_aligned 90.Fa "bus_dmaengine_t dmaengine" 91.Fa "bus_addr_t dst1" 92.Fa "bus_addr_t dst2" 93.Fa "bus_addr_t src1" 94.Fa "bus_addr_t src2" 95.Fa "bus_dmaengine_callback_t callback_fn" 96.Fa "void *callback_arg" 97.Fa "uint32_t flags" 98.Fc 99.Ft struct bus_dmadesc * 100.Fo ioat_blockfill 101.Fa "bus_dmaengine_t dmaengine" 102.Fa "bus_addr_t dst" 103.Fa "uint64_t fillpattern" 104.Fa "bus_size_t len" 105.Fa "bus_dmaengine_callback_t callback_fn" 106.Fa "void *callback_arg" 107.Fa "uint32_t flags" 108.Fc 109.Ft struct bus_dmadesc * 110.Fo ioat_null 111.Fa "bus_dmaengine_t dmaengine" 112.Fa "bus_dmaengine_callback_t callback_fn" 113.Fa "void *callback_arg" 114.Fa "uint32_t flags" 115.Fc 116.Sh DESCRIPTION 117The 118.Nm 119driver provides a kernel API to a variety of DMA engines on some Intel server 120platforms. 121.Pp 122There is a number of DMA channels per CPU package. 123(Typically 4 or 8.) 124Each may be used independently. 125Operations on a single channel proceed sequentially. 126.Pp 127Blockfill operations can be used to write a 64-bit pattern to memory. 128.Pp 129Copy operations can be used to offload memory copies to the DMA engines. 130.Pp 131Null operations do nothing, but may be used to test the interrupt and callback 132mechanism. 133.Pp 134All operations can optionally trigger an interrupt at completion with the 135.Ar DMA_EN_INT 136flag. 137For example, a user might submit multiple operations to the same channel and 138only enable an interrupt and callback for the last operation. 139.Pp 140The hardware can delay and coalesce interrupts on a given channel for a 141configurable period of time, in microseconds. 142This may be desired to reduce the processing and interrupt overhead per 143descriptor, especially for workflows consisting of many small operations. 144Software can control this on a per-channel basis with the 145.Fn ioat_set_interrupt_coalesce 146API. 147The 148.Fn ioat_get_max_coalesce_period 149API can be used to determine the maximum coalescing period supported by the 150hardware, in microseconds. 151Current platforms support up to a 16.383 millisecond coalescing period. 152Optimal configuration will vary by workflow and desired operation latency. 153.Pp 154All operations are safe to use in a non-blocking context with the 155.Ar DMA_NO_WAIT 156flag. 157(Of course, allocations may fail and operations requested with 158.Ar DMA_NO_WAIT 159may return NULL.) 160.Pp 161All operations, as well as 162.Fn ioat_get_dmaengine , 163can return NULL in special circumstances. 164For example, if the 165.Nm 166driver is being unloaded, or the administrator has induced a hardware reset, or 167a usage error has resulted in a hardware error state that needs to be recovered 168from. 169.Pp 170It is invalid to attempt to submit new DMA operations in a 171.Fa bus_dmaengine_callback_t 172context. 173.Sh USAGE 174A typical user will lookup the DMA engine object for a given channel with 175.Fn ioat_get_dmaengine . 176When the user wants to offload a copy, they will first 177.Fn ioat_acquire 178the 179.Ar bus_dmaengine_t 180object for exclusive access to enqueue operations on that channel. 181Then, they will submit one or more operations using 182.Fn ioat_blockfill , 183.Fn ioat_copy , 184or 185.Fn ioat_null . 186After queuing one or more individual DMA operations, they will 187.Fn ioat_release 188the 189.Ar bus_dmaengine_t 190to drop their exclusive access to the channel. 191The routine they provided for the 192.Fa callback_fn 193argument will be invoked with the provided 194.Fa callback_arg 195when the operation is complete. 196When they are finished with the 197.Ar bus_dmaengine_t , 198the user should 199.Fn ioat_put_dmaengine . 200.Pp 201Users MUST NOT block between 202.Fn ioat_acquire 203and 204.Fn ioat_release . 205Users SHOULD NOT hold 206.Ar bus_dmaengine_t 207references for a very long time to enable fault recovery and kernel module 208unload. 209.Pp 210For an example of usage, see 211.Pa src/sys/dev/ioat/ioat_test.c . 212.Sh FILES 213.Bl -tag 214.It Pa /dev/ioat_test 215test device for 216.Xr ioatcontrol 8 217.El 218.Sh SEE ALSO 219.Xr ioatcontrol 8 220.Sh HISTORY 221The 222.Nm 223driver first appeared in 224.Fx 11.0 . 225.Sh AUTHORS 226The 227.Nm 228driver was developed by 229.An \&Jim Harris Aq Mt jimharris@FreeBSD.org , 230.An \&Carl Delsey Aq Mt carl.r.delsey@intel.com , 231and 232.An \&Conrad Meyer Aq Mt cem@FreeBSD.org . 233This manual page was written by 234.An \&Conrad Meyer Aq Mt cem@FreeBSD.org . 235.Sh CAVEATS 236Copy operation takes bus addresses as parameters, not virtual addresses. 237.Pp 238Buffers for individual copy operations must be physically contiguous. 239.Pp 240Copies larger than max transfer size (1MB, but may vary by hardware) are not 241supported. 242Future versions will likely support this by breaking up the transfer into 243smaller sizes. 244.Sh BUGS 245The 246.Nm 247driver only supports blockfill, copy, and null operations at this time. 248The driver does not yet support advanced DMA modes, such as XOR, that some 249I/OAT devices support. 250