1.\" Copyright (c) 2015 EMC / Isilon Storage Division 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd December 14, 2015 28.Dt IOAT 4 29.Os 30.Sh NAME 31.Nm I/OAT 32.Nd Intel I/O Acceleration Technology 33.Sh SYNOPSIS 34To compile this driver into your kernel, 35place the following line in your kernel configuration file: 36.Bd -ragged -offset indent 37.Cd "device ioat" 38.Ed 39.Pp 40Or, to load the driver as a module at boot, place the following line in 41.Xr loader.conf 5 : 42.Bd -literal -offset indent 43ioat_load="YES" 44.Ed 45.Pp 46In 47.Xr loader.conf 5 : 48.Pp 49.Cd hw.ioat.force_legacy_interrupts=0 50.Pp 51In 52.Xr loader.conf 5 or 53.Xr sysctl.conf 5 : 54.Pp 55.Cd hw.ioat.enable_ioat_test=0 56.Cd hw.ioat.debug_level=0 57(only critical errors; maximum of 3) 58.Pp 59.Ft typedef void 60.Fn (*bus_dmaengine_callback_t) "void *arg" "int error" 61.Pp 62.Ft bus_dmaengine_t 63.Fn ioat_get_dmaengine "uint32_t channel_index" 64.Ft void 65.Fn ioat_put_dmaengine "bus_dmaengine_t dmaengine" 66.Ft int 67.Fn ioat_set_interrupt_coalesce "bus_dmaengine_t dmaengine" "uint16_t delay" 68.Ft uint16_t 69.Fn ioat_get_max_coalesce_period "bus_dmaengine_t dmaengine" 70.Ft void 71.Fn ioat_acquire "bus_dmaengine_t dmaengine" 72.Ft void 73.Fn ioat_release "bus_dmaengine_t dmaengine" 74.Ft struct bus_dmadesc * 75.Fo ioat_copy 76.Fa "bus_dmaengine_t dmaengine" 77.Fa "bus_addr_t dst" 78.Fa "bus_addr_t src" 79.Fa "bus_size_t len" 80.Fa "bus_dmaengine_callback_t callback_fn" 81.Fa "void *callback_arg" 82.Fa "uint32_t flags" 83.Fc 84.Ft struct bus_dmadesc * 85.Fo ioat_copy_8k_aligned 86.Fa "bus_dmaengine_t dmaengine" 87.Fa "bus_addr_t dst1" 88.Fa "bus_addr_t dst2" 89.Fa "bus_addr_t src1" 90.Fa "bus_addr_t src2" 91.Fa "bus_dmaengine_callback_t callback_fn" 92.Fa "void *callback_arg" 93.Fa "uint32_t flags" 94.Fc 95.Ft struct bus_dmadesc * 96.Fo ioat_blockfill 97.Fa "bus_dmaengine_t dmaengine" 98.Fa "bus_addr_t dst" 99.Fa "uint64_t fillpattern" 100.Fa "bus_size_t len" 101.Fa "bus_dmaengine_callback_t callback_fn" 102.Fa "void *callback_arg" 103.Fa "uint32_t flags" 104.Fc 105.Ft struct bus_dmadesc * 106.Fo ioat_null 107.Fa "bus_dmaengine_t dmaengine" 108.Fa "bus_dmaengine_callback_t callback_fn" 109.Fa "void *callback_arg" 110.Fa "uint32_t flags" 111.Fc 112.Sh DESCRIPTION 113The 114.Nm 115driver provides a kernel API to a variety of DMA engines on some Intel server 116platforms. 117.Pp 118There is a number of DMA channels per CPU package. 119(Typically 4 or 8.) 120Each may be used independently. 121Operations on a single channel proceed sequentially. 122.Pp 123Blockfill operations can be used to write a 64-bit pattern to memory. 124.Pp 125Copy operations can be used to offload memory copies to the DMA engines. 126.Pp 127Null operations do nothing, but may be used to test the interrupt and callback 128mechanism. 129.Pp 130All operations can optionally trigger an interrupt at completion with the 131.Ar DMA_EN_INT 132flag. 133For example, a user might submit multiple operations to the same channel and 134only enable an interrupt and callback for the last operation. 135.Pp 136The hardware can delay and coalesce interrupts on a given channel for a 137configurable period of time, in microseconds. 138This may be desired to reduce the processing and interrupt overhead per 139descriptor, especially for workflows consisting of many small operations. 140Software can control this on a per-channel basis with the 141.Fn ioat_set_interrupt_coalesce 142API. 143The 144.Fn ioat_get_max_coalesce_period 145API can be used to determine the maximum coalescing period supported by the 146hardware, in microseconds. 147Current platforms support up to a 16.383 millisecond coalescing period. 148Optimal configuration will vary by workflow and desired operation latency. 149.Pp 150All operations are safe to use in a non-blocking context with the 151.Ar DMA_NO_WAIT 152flag. 153(Of course, allocations may fail and operations requested with 154.Ar DMA_NO_WAIT 155may return NULL.) 156.Pp 157All operations, as well as 158.Fn ioat_get_dmaengine , 159can return NULL in special circumstances. 160For example, if the 161.Nm 162driver is being unloaded, or the administrator has induced a hardware reset, or 163a usage error has resulted in a hardware error state that needs to be recovered 164from. 165.Pp 166It is invalid to attempt to submit new DMA operations in a 167.Fa bus_dmaengine_callback_t 168context. 169.Sh USAGE 170A typical user will lookup the DMA engine object for a given channel with 171.Fn ioat_get_dmaengine . 172When the user wants to offload a copy, they will first 173.Fn ioat_acquire 174the 175.Ar bus_dmaengine_t 176object for exclusive access to enqueue operations on that channel. 177Then, they will submit one or more operations using 178.Fn ioat_blockfill , 179.Fn ioat_copy , 180or 181.Fn ioat_null . 182After queuing one or more individual DMA operations, they will 183.Fn ioat_release 184the 185.Ar bus_dmaengine_t 186to drop their exclusive access to the channel. 187The routine they provided for the 188.Fa callback_fn 189argument will be invoked with the provided 190.Fa callback_arg 191when the operation is complete. 192When they are finished with the 193.Ar bus_dmaengine_t , 194the user should 195.Fn ioat_put_dmaengine . 196.Pp 197Users MUST NOT block between 198.Fn ioat_acquire 199and 200.Fn ioat_release . 201Users SHOULD NOT hold 202.Ar bus_dmaengine_t 203references for a very long time to enable fault recovery and kernel module 204unload. 205.Pp 206For an example of usage, see 207.Pa src/sys/dev/ioat/ioat_test.c . 208.Sh FILES 209.Bl -tag 210.It Pa /dev/ioat_test 211test device for 212.Xr ioatcontrol 8 213.El 214.Sh SEE ALSO 215.Xr ioatcontrol 8 216.Sh HISTORY 217The 218.Nm 219driver first appeared in 220.Fx 11.0 . 221.Sh AUTHORS 222The 223.Nm 224driver was developed by 225.An \&Jim Harris Aq Mt jimharris@FreeBSD.org , 226.An \&Carl Delsey Aq Mt carl.r.delsey@intel.com , 227and 228.An \&Conrad Meyer Aq Mt cem@FreeBSD.org . 229This manual page was written by 230.An \&Conrad Meyer Aq Mt cem@FreeBSD.org . 231.Sh CAVEATS 232Copy operation takes bus addresses as parameters, not virtual addresses. 233.Pp 234Buffers for individual copy operations must be physically contiguous. 235.Pp 236Copies larger than max transfer size (1MB, but may vary by hardware) are not 237supported. 238Future versions will likely support this by breaking up the transfer into 239smaller sizes. 240.Sh BUGS 241The 242.Nm 243driver only supports blockfill, copy, and null operations at this time. 244The driver does not yet support advanced DMA modes, such as XOR, that some 245I/OAT devices support. 246