1.\" 2.\" SPDX-License-Identifier: BSD-2-Clause 3.\" 4.\" Copyright (c) 2026 Abdelkader Boudih <seuros@FreeBSD.org> 5.\" 6.Dd September 7, 2026 7.Dt INTEL_PMC 4 8.Os 9.Sh NAME 10.Nm intel_pmc 11.Nd Intel Performance Management Controller driver 12.Sh SYNOPSIS 13.Cd "device intel_pmc" 14.Sh DESCRIPTION 15The 16.Nm 17driver exposes information and controls from the Performance 18Management Controller (PMC) of Intel platforms. 19Presently, it supports the Intel Sunrise Point platform (Skylake CPU 20generation), providing access to debug information and controls 21related to S0ix (Modern Standby). 22.Pp 23The cumulative time spent in low power mode while in S0 is reported, 24and the administrator can force the platform to ignore IP blocks 25whose Latency Tolerance Reporting (LTR) prevents the platform from 26entering S0ix. 27.Sh HARDWARE 28The 29.Nm 30driver supports the PMC block found in the following Intel Platform 31Controller Hubs: 32.Pp 33.Bl -bullet -compact 34.It 35Intel Sunrise Point-LP PMC (6th/7th Gen Core mobile, PCI ID 0x8086:0x9d21) 36.It 37Intel Sunrise Point-H PMC (6th/7th Gen Core desktop/server, 38PCI ID 0x8086:0xa121) 39.El 40.Sh SYSCTLS 41The following 42.Xr sysctl 8 43variables are available: 44.Bl -tag -width indent 45.It Va dev.intel_pmc.%d.ltr_ignore Pq read-write 46Latency Tolerance Reporting (LTR) ignore mask. 47Each bit corresponds to one IP block (bits 0-16). 48Setting a bit tells the PMC to ignore that IP's LTR requirements, 49allowing S0ix entry even if the IP would otherwise block it. 50A clear bit means the IP's requirements are considered and can 51prevent S0ix. 52.Pp 53Sunrise Point bit assignments: 54SOUTHPORT_A, SOUTHPORT_B, SATA, GIGABIT_ETHERNET, XHCI, reserved, 55ME, EVA, SOUTHPORT_C, HD_AUDIO, LPSS, SOUTHPORT_D, SOUTHPORT_E, 56CAMERA, ESPI, SCC, ISH. 57.It Va dev.intel_pmc.%d.slp_s0_residency Pq read-only 58Cumulative time in microseconds that the SLP_S0 signal has been 59asserted (100\ us per counter step). 60Per the datasheet, SLP_S0 asserts when the PCH is idle and the 61processor is in C10 state. 62A value that never advances indicates S0ix transitions are not occurring. 63.Pp 64The counter is 32-bit and wraps after approximately 5 days of 65cumulative S0ix residency. 66.El 67.Sh SEE ALSO 68.Xr acpi 4 , 69.Xr pci 4 , 70.Xr sysctl 8 71.Pp 72Intel 100 Series Chipset Family PCH Datasheet, Volume 2, Section 4.3. 73.Sh HISTORY 74The 75.Nm 76driver first appeared in 77.Fx 16.0 . 78.Sh AUTHORS 79.An Abdelkader Boudih Aq Mt seuros@FreeBSD.org 80.Sh CAVEATS 81Only Sunrise Point PCH is supported. 82Other PCH generations (Cannon Point, Tiger Lake, etc.) have different 83register layouts and are not handled by this driver. 84