1.\" Copyright (c) 1998, Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd August 6, 1998 28.Dt IICBUS 4 29.Os FreeBSD 30.Sh NAME 31.Nm iicbus 32.Nd 33I2C bus system 34.Sh SYNOPSIS 35.Cd "device iicbus" 36.Cd "device iicbb" 37.Pp 38.Cd "device iic" 39.Cd "device ic" 40.Cd "device iicsmb" 41.Sh DESCRIPTION 42The 43.Em iicbus 44system provides a uniform, modular and architecture-independent 45system for the implementation of drivers to control various I2C devices 46and to utilize different I2C controllers. 47.Sh I2C 48I2C is an acronym for Inter Integrated Circuit bus. 49The I2C bus was developed 50in the early 1980's by Philips semiconductors. 51It's purpose was to provide an 52easy way to connect a CPU to peripheral chips in a TV-set. 53.Pp 54The BUS physically consists of 2 active wires and a ground connection. 55The active wires, SDA and SCL, are both bidirectional. 56Where SDA is the 57Serial DAta line and SCL is the Serial CLock line. 58 59Every component hooked up to the bus has its own unique address whether it 60is a CPU, LCD driver, memory, or complex function chip. 61Each of these chips 62can act as a receiver and/or transmitter depending on its functionality. 63Obviously an LCD driver is only a receiver, while a memory or I/O chip can 64both be transmitter and receiver. 65Furthermore there may be one or 66more BUS MASTERs. 67 68The BUS MASTER is the chip issuing the commands on the BUS. 69In the I2C protocol 70specification it is stated that the IC that initiates a data transfer on the 71bus is considered the BUS MASTER. 72At that time all the others are regarded to 73as the BUS SLAVEs. 74As mentioned before, the IC bus is a Multi-MASTER BUS. 75This means that more than one IC capable of initiating data transfer can be 76connected to it. 77.Sh DEVICES 78Some I2C device drivers are available: 79.Pp 80.Bl -column "Device drivers" -compact 81.It Em Devices Ta Em Description 82.It Sy iic Ta "general i/o operation" 83.It Sy ic Ta "network IP interface" 84.It Sy iicsmb Ta "I2C to SMB software bridge" 85.El 86.Sh INTERFACES 87The I2C protocol may be implemented by hardware or software. 88Software 89interfaces rely on very simple hardware, usually two lines 90twiddled by 2 registers. 91Hardware interfaces are more intelligent and receive 928-bit characters they write to the bus according to the I2C protocol. 93 94I2C interfaces may act on the bus as slave devices, allowing spontaneous 95bidirectional communications, thanks to the multi-master capabilities of the 96I2C protocol. 97 98Some I2C interfaces are available: 99.Pp 100.Bl -column "Interface drivers" -compact 101.It Em Interface Ta Em Description 102.It Sy pcf Ta "Philips PCF8584 master/slave interface" 103.It Sy iicbb Ta "generic bit-banging master-only driver" 104.It Sy lpbb Ta "parallel port specific bit-banging interface" 105.It Sy bktr Ta "Brooktree848 video chipset, hardware and software master-only interface" 106.El 107.Sh SEE ALSO 108.Xr iicbb 4 , 109.Xr lpbb 4 , 110.Xr pcf 4 111.Sh HISTORY 112The 113.Nm 114manual page first appeared in 115.Fx 3.0 . 116.Sh AUTHORS 117This 118manual page was written by 119.An Nicolas Souchu . 120