1.\" Copyright (c) 1998, Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" 26.Dd August 6, 1998 27.Dt IICBUS 4 28.Os FreeBSD 29.Sh NAME 30.Nm iicbus 31.Nd 32I2C bus system 33.Sh SYNOPSIS 34.Cd "controller iicbus0" 35.Cd "controller iicbb0" 36.Pp 37.Cd "device iic0 at iicbus?" 38.Cd "device ic0 at iicbus?" 39.Cd "device iicsmb0 at iicbus?" 40.Sh DESCRIPTION 41The 42.Em iicbus 43system provides a uniform, modular and architecture-independent 44system for the implementation of drivers to control various I2C devices 45and to utilize different I2C controllers. 46.Sh I2C 47I2C is an acronym for Inter Integrated Circuit bus. The I2C bus was developed 48in the early 1980's by Philips semiconductors. It's purpose was to provide an 49easy way to connect a CPU to peripheral chips in a TV-set. 50.Pp 51The BUS physically consists of 2 active wires and a ground connection. 52The active wires, SDA and SCL, are both bidirectional. Where SDA is the 53Serial DAta line and SCL is the Serial CLock line. 54 55Every component hooked up to the bus has its own unique address whether it 56is a CPU, LCD driver, memory, or complex function chip. Each of these chips 57can act as a receiver and/or transmitter depending on it's functionality. 58Obviously an LCD driver is only a receiver, while a memory or I/O chip can 59both be transmitter and receiver. Furthermore there may be one or 60more BUS MASTER's. 61 62The BUS MASTER is the chip issuing the commands on the BUS. In the I2C protocol 63specification it is stated that the IC that initiates a data transfer on the 64bus is considered the BUS MASTER. At that time all the others are regarded to 65as the BUS SLAVEs. As mentioned before, the IC bus is a Multi-MASTER BUS. 66This means that more than one IC capable of initiating data transfer can be 67connected to it. 68.Sh DEVICES 69Some I2C device drivers are available: 70.Pp 71.Bl -column "Device drivers" -compact 72.It Em Devices Ta Em Description 73.It Sy iic Ta "general i/o operation" 74.It Sy ic Ta "network IP interface" 75.It Sy iicsmb Ta "I2C to SMB software bridge" 76.El 77.Sh INTERFACES 78The I2C protocol may be implemented by hardware or software. Software 79interfaces rely on very simple hardware, usually two lines 80twiddled by 2 registers. Hardware interfaces are more intelligent and receive 818-bit characters they write to the bus according to the I2C protocol. 82 83I2C interfaces may act on the bus as slave devices, allowing spontaneous 84bidirectional communications, thanks to the mutli-master capabilities of the 85I2C protocol. 86 87Some I2C interfaces are available: 88.Pp 89.Bl -column "Interface drivers" -compact 90.It Em Interface Ta Em Description 91.It Sy pcf Ta "Philips PCF8584 master/slave interface" 92.It Sy iicbb Ta "generic bit-banging master-only driver" 93.It Sy lpbb Ta "parallel port specific bit-banging interface" 94.It Sy bktr Ta "Brooktree848 video chipset, hardware and software master-only interface" 95.El 96.Sh SEE ALSO 97.Xr pcf 4 , 98.Xr iicbb 4 , 99.Xr lpbb 4 100.Sh HISTORY 101The 102.Nm 103manual page first appeared in 104.Fx 3.0 . 105.Sh AUTHOR 106This 107manual page was written by 108.An Nicolas Souchu . 109