1.\" 2.\" Copyright (c) 2012 Sean Bruno <sbruno@freebsd.org> 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24.\" SUCH DAMAGE. 25.\" 26.Dd April 21, 2020 27.Dt EST 4 28.Os 29.Sh NAME 30.Nm est 31.Nd Enhanced Speedstep Technology 32.Sh SYNOPSIS 33To compile this capability into your kernel 34place the following line in your kernel 35configuration file: 36.Bd -ragged -offset indent 37.Cd "device cpufreq" 38.Ed 39.Sh DESCRIPTION 40The 41.Nm 42interface provides support for the Intel Enhanced Speedstep Technology. 43.Pp 44Note that 45.Nm 46capabilities are automatically loaded by the 47.Xr cpufreq 4 48driver. 49.Sh LOADER TUNABLES 50The 51.Nm 52interface is intended to allow 53.Xr cpufreq 4 54to access and implement Intel Enhanced SpeedStep Technology via 55.Xr acpi 4 56and the acpi_perf interface accessors. 57If the default settings are not optimal, the following sysctls can be 58used to modify or monitor 59.Nm 60behavior. 61.Bl -tag -width indent 62.It hw.est.msr_info 63Attempt to infer information from direct probing of the msr. 64Should only be used in diagnostic cases. 65.Pq default 0 66.It hw.est.strict 67Validate frequency requested is accepted by the CPU when set. 68It appears that this will only work on single core cpus. 69.Pq default 0 70.El 71.Sh SYSCTL VARIABLES 72The following 73.Xr sysctl 8 74values are available 75.Bl -tag -width indent 76.It Va dev.est.%d.%desc 77Description of support, almost always Enhanced SpeedStep Frequency Control. 78.It dev.est.0.%desc: Enhanced SpeedStep Frequency Control 79.It Va dev.est.%d.%driver 80Driver in use, always est. 81.It dev.est.0.%driver: est 82.It Va dev.est.%d.%parent 83The CPU that is exposing these frequencies. 84For example 85.Va cpu0 . 86.It dev.est.0.%parent: cpu0 87.It Va dev.est.%d.freq_settings . 88The valid frequencies that are allowed by this CPU and their step values. 89.It dev.est.0.freq_settings: 2201/45000 2200/45000 2000/39581 1900/37387 901800/34806 1700/32703 1600/30227 1500/28212 1400/25828 1300/23900 1200/21613 911100/19775 1000/17582 900/15437 800/13723 92.El 93.Sh DIAGNOSTICS 94.Bl -diag 95.It "est%d: <Enhanced SpeedStep Frequency Control> on cpu%d" 96.Pp 97Indicates normal startup of this interface. 98.It "est: CPU supports Enhanced Speedstep, but is not recognized." 99.It "est: cpu_vendor GenuineIntel, msr 471c471c0600471c" 100.It "device_attach: est%d attach returned 6" 101.Pp 102Indicates all attempts to attach to this interface have failed. 103This usually indicates an improper BIOS setting restricting O/S 104control of the CPU speeds. 105Consult your BIOS documentation for more details. 106.El 107.Sh COMPATIBILITY 108.Nm 109is only found on supported Intel CPUs. 110.Sh SEE ALSO 111.Xr cpufreq 4 112.Rs 113.%T "Intel 64 and IA-32 Architectures Software Developer Manuals" 114.%U "http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" 115.Re 116.Sh AUTHORS 117This manual page was written by 118.An Sean Bruno Aq Mt sbruno@FreeBSD.org . 119