1.\"- 2.\" Copyright (c) 2012 Robert N. M. Watson 3.\" All rights reserved. 4.\" 5.\" This software was developed by SRI International and the University of 6.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7.\" ("CTSRD"), as part of the DARPA CRASH research programme. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28.\" SUCH DAMAGE. 29.\" 30.Dd August 18, 2012 31.Dt ALTERA_SDCARD 4 32.Os 33.Sh NAME 34.Nm altera_sdcard 35.Nd driver for the Altera University Program Secure Data Card IP Core 36.Sh SYNOPSIS 37.Cd "device altera_sdcard" 38.Pp 39In 40.Pa /boot/device.hints : 41.Cd hint.altera_sdcardc.0.at="nexus0" 42.Cd hint.altera_sdcardc.0.maddr=0x7f008000 43.Cd hint.altera_sdcardc.0.msize=0x400 44.Sh DESCRIPTION 45The 46.Nm 47device driver provides support for the Altera University Program Secure Data 48Card (SD Card) IP Core device. 49A controller device, 50.Li altera_sdcardcX , 51will be attached during boot. 52Inserted disks are presented as 53.Xr disk 9 54devices, 55.Li altera_sdcardX , 56corresponding to the controller number. 57.Sh HARDWARE 58The current version of the 59.Nm 60driver supports the SD Card IP core as described in the August 2011 version of 61Altera's documentation. 62The core supports only cards up to 2G (CSD 0); larger cards, or cards using 63newer CSD versions, will not be detected. 64The IP core has two key limitations: a lack of interrupt support, requiring 65timer-driven polling to detect I/O completion, and support for only single 66512-byte block read and write operations at a time. 67The combined effect of those two limits is that the system clock rate, 68.Dv HZ , 69must be set to at least 200 in order to accomplish the maximum 100KB/s data 70rate supported by the IP core. 71.Sh SEE ALSO 72.Xr disk 9 73.Rs 74.%T Altera University Program Secure Data Card IP Core 75.%D August 2011 76.%I Altera Corporation - University Program 77.%U ftp://ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/SD_Card_Interface_for_SoPC_Builder.pdf 78.Re 79.Sh HISTORY 80The 81.Nm 82device driver first appeared in 83.Fx 10.0 . 84.Sh AUTHORS 85The 86.Nm 87device driver and this manual page were 88developed by SRI International and the University of Cambridge Computer 89Laboratory under DARPA/AFRL contract 90.Pq FA8750-10-C-0237 91.Pq Do CTSRD Dc , 92as part of the DARPA CRASH research programme. 93This device driver was written by 94.An Robert N. M. Watson . 95.Sh BUGS 96.Nm 97contains a number of work-arounds for IP core bugs. 98Perhaps most critically, 99.Nm 100ignores the CRC error bit returned in the RR1 register, which appears to be 101unexpectedly set by the IP core. 102.Pp 103.Nm 104uses fixed polling intervals are used for card insertion/removal and 105I/O completion detection; an adaptive strategy might improve performance by 106reducing the latency to detecting completed I/O. 107However, in our experiments, using polling rates greater than 200 times a 108second did not improve performance. 109.Pp 110.Nm 111supports only a 112.Li nexus 113bus attachment, which is appropriate for system-on-chip busses such as 114Altera's Avalon bus. 115If the IP core is configured off of another bus type, then additional bus 116attachments will be required. 117