1.\"- 2.\" Copyright (c) 2012 Robert N. M. Watson 3.\" All rights reserved. 4.\" 5.\" This software was developed by SRI International and the University of 6.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7.\" ("CTSRD"), as part of the DARPA CRASH research programme. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28.\" SUCH DAMAGE. 29.\" 30.\" $FreeBSD$ 31.\" 32.Dd August 18, 2012 33.Dt ALTERA_SDCARD 4 34.Os 35.Sh NAME 36.Nm altera_sdcard 37.Nd driver for the Altera University Program Secure Data Card IP Core 38.Sh SYNOPSIS 39.Cd "device altera_sdcard" 40.Pp 41In 42.Pa /boot/device.hints : 43.Cd hint.altera_sdcardc.0.at="nexus0" 44.Cd hint.altera_sdcardc.0.maddr=0x7f008000 45.Cd hint.altera_sdcardc.0.msize=0x400 46.Sh DESCRIPTION 47The 48.Nm 49device driver provides support for the Altera University Program Secure Data 50Card (SD Card) IP Core device. 51A controller device, 52.Li altera_sdcardcX , 53will be attached during boot. 54Inserted disks are presented as 55.Xr disk 9 56devices, 57.Li altera_sdcardX , 58corresponding to the controller number. 59.Sh HARDWARE 60The current version of the 61.Nm 62driver supports the SD Card IP core as described in the August 2011 version of 63Altera's documentation. 64The core supports only cards up to 2G (CSD 0); larger cards, or cards using 65newer CSD versions, will not be detected. 66The IP core has two key limitations: a lack of interrupt support, requiring 67timer-driven polling to detect I/O completion, and support for only single 68512-byte block read and write operations at a time. 69The combined effect of those two limits is that the system clock rate, 70.Dv HZ , 71must be set to at least 200 in order to accomplish the maximum 100KB/s data 72rate supported by the IP core. 73.Sh SEE ALSO 74.Xr disk 9 75.Rs 76.%T Altera University Program Secure Data Card IP Core 77.%D August 2011 78.%I Altera Corporation - University Program 79.%U ftp://ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/SD_Card_Interface_for_SoPC_Builder.pdf 80.Re 81.Sh HISTORY 82The 83.Nm 84device driver first appeared in 85.Fx 10.0 . 86.Sh AUTHORS 87The 88.Nm 89device driver and this manual page were 90developed by SRI International and the University of Cambridge Computer 91Laboratory under DARPA/AFRL contract 92.Pq FA8750-10-C-0237 93.Pq Do CTSRD Dc , 94as part of the DARPA CRASH research programme. 95This device driver was written by 96.An Robert N. M. Watson . 97.Sh BUGS 98.Nm 99contains a number of work-arounds for IP core bugs. 100Perhaps most critically, 101.Nm 102ignores the CRC error bit returned in the RR1 register, which appears to be 103unexpectedly set by the IP core. 104.Pp 105.Nm 106uses fixed polling intervals are used for card insertion/removal and 107I/O completion detection; an adaptive strategy might improve performance by 108reducing the latency to detecting completed I/O. 109However, in our experiments, using polling rates greater than 200 times a 110second did not improve performance. 111.Pp 112.Nm 113supports only a 114.Li nexus 115bus attachment, which is appropriate for system-on-chip busses such as 116Altera's Avalon bus. 117If the IP core is configured off of another bus type, then additional bus 118attachments will be required. 119