1.\" 2.\" Copyright (c) 1995, 1996, 1997, 1998, 2000 3.\" Justin T. Gibbs. All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 3. The name of the author may not be used to endorse or promote products 14.\" derived from this software without specific prior written permission. 15.\" 16.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd February 15, 2017 30.Dt AHC 4 31.Os 32.Sh NAME 33.Nm ahc 34.Nd Adaptec VL/ISA/PCI SCSI host adapter driver 35.Sh SYNOPSIS 36To compile this driver into the kernel, 37place the following lines in your 38kernel configuration file: 39.Bd -ragged -offset indent 40.Cd "device scbus" 41.Cd "device ahc" 42.Pp 43For one or more PCI cards: 44.Cd "device pci" 45.Pp 46To allow PCI adapters to use memory mapped I/O if enabled: 47.Cd options AHC_ALLOW_MEMIO 48.Pp 49To configure one or more controllers to assume the target role: 50.Cd options AHC_TMODE_ENABLE <bitmask of units> 51.Ed 52.Pp 53Alternatively, to load the driver as a 54module at boot time, place the following lines in 55.Xr loader.conf 5 : 56.Bd -literal -offset indent 57ahc_load="YES" 58ahc_isa_load="YES" 59ahc_pci_load="YES" 60.Ed 61.Sh DESCRIPTION 62This driver provides access to the 63.Tn SCSI 64bus(es) connected to the Adaptec AIC77xx and AIC78xx 65host adapter chips. 66.Pp 67Driver features include support for twin and wide busses, 68fast, ultra or ultra2 synchronous transfers depending on controller type, 69tagged queueing, SCB paging, and target mode. 70.Pp 71Memory mapped I/O can be enabled for PCI devices with the 72.Dq Dv AHC_ALLOW_MEMIO 73configuration option. 74Memory mapped I/O is more efficient than the alternative, programmed I/O. 75Most PCI BIOSes will map devices so that either technique for communicating 76with the card is available. 77In some cases, 78usually when the PCI device is sitting behind a PCI->PCI bridge, 79the BIOS may fail to properly initialize the chip for memory mapped I/O. 80The typical symptom of this problem is a system hang if memory mapped I/O 81is attempted. 82Most modern motherboards perform the initialization correctly and work fine 83with this option enabled. 84.Pp 85Individual controllers may be configured to operate in the target role 86through the 87.Dq Dv AHC_TMODE_ENABLE 88configuration option. 89The value assigned to this option should be a bitmap 90of all units where target mode is desired. 91For example, a value of 0x25, would enable target mode on units 0, 2, and 5. 92A value of 0x8a enables it for units 1, 3, and 7. 93.Pp 94Per target configuration performed in the 95.Tn SCSI-Select 96menu, accessible at boot 97is honored by this driver. 98This includes synchronous/asynchronous transfers, 99maximum synchronous negotiation rate, 100wide transfers, 101disconnection, 102the host adapter's SCSI ID. 103For systems that store non-volatile settings in a system specific manner 104rather than a serial eeprom directly connected to the aic7xxx controller, 105the 106.Tn BIOS 107must be enabled for the driver to access this information. 108This restriction applies to 109many chip-down motherboard configurations. 110.Pp 111Performance and feature sets vary throughout the aic7xxx product line. 112The following table provides a comparison of the different chips supported 113by the 114.Nm 115driver. 116Note that wide and twin channel features, although always supported 117by a particular chip, may be disabled in a particular motherboard or card 118design. 119.Bd -ragged -offset indent 120.Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X" 121.It Em "Chip" Ta "MIPS" Ta "Bus" Ta "MaxSync" Ta "MaxWidth" Ta "SCBs" Ta "Features" 122.It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1" 123.It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta "" 124.It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta "" 125.It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta "" 126.It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "" 127.It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8" 128.It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8" 129.It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8" 130.It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5" 131.It "aic7895C" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 8" 132.It "aic7896" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8" 133.It "aic7897" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8" 134.It "aic7899" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8" 135.El 136.Pp 137.Bl -enum -compact 138.It 139Multiplexed Twin Channel Device - One controller servicing two busses. 140.It 141Multi-function Twin Channel Device - Two controllers on one chip. 142.It 143Command Channel Secondary DMA Engine - Allows scatter gather list and 144SCB prefetch. 145.It 14664 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA. 147.It 148Block Move Instruction Support - Doubles the speed of certain sequencer 149operations. 150.It 151.Sq Bayonet 152style Scatter Gather Engine - Improves S/G prefetch performance. 153.It 154Queuing Registers - Allows queueing of new transactions without pausing the 155sequencer. 156.It 157Multiple Target IDs - Allows the controller to respond to selection as a 158target on multiple SCSI IDs. 159.El 160.Ed 161.Sh HARDWARE 162The 163.Nm 164driver supports the following 165.Tn SCSI 166host adapter chips and 167.Tn SCSI 168controller cards: 169.Pp 170.Bl -bullet -compact 171.It 172Adaptec 173.Tn AIC7770 174host adapter chip 175.It 176Adaptec 177.Tn AIC7850 178host adapter chip 179.It 180Adaptec 181.Tn AIC7860 182host adapter chip 183.It 184Adaptec 185.Tn AIC7870 186host adapter chip 187.It 188Adaptec 189.Tn AIC7880 190host adapter chip 191.It 192Adaptec 193.Tn AIC7890 194host adapter chip 195.It 196Adaptec 197.Tn AIC7891 198host adapter chip 199.It 200Adaptec 201.Tn AIC7892 202host adapter chip 203.It 204Adaptec 205.Tn AIC7895 206host adapter chip 207.It 208Adaptec 209.Tn AIC7896 210host adapter chip 211.It 212Adaptec 213.Tn AIC7897 214host adapter chip 215.It 216Adaptec 217.Tn AIC7899 218host adapter chip 219.It 220Adaptec 221.Tn 274X(W) 222.It 223Adaptec 224.Tn 274X(T) 225.It 226Adaptec 227.Tn 2910 228.It 229Adaptec 230.Tn 2915 231.It 232Adaptec 233.Tn 2920C 234.It 235Adaptec 236.Tn 2930C 237.It 238Adaptec 239.Tn 2930U2 240.It 241Adaptec 242.Tn 2940 243.It 244Adaptec 245.Tn 2940J 246.It 247Adaptec 248.Tn 2940N 249.It 250Adaptec 251.Tn 2940U 252.It 253Adaptec 254.Tn 2940AU 255.It 256Adaptec 257.Tn 2940UW 258.It 259Adaptec 260.Tn 2940UW Dual 261.It 262Adaptec 263.Tn 2940UW Pro 264.It 265Adaptec 266.Tn 2940U2W 267.It 268Adaptec 269.Tn 2940U2B 270.It 271Adaptec 272.Tn 2950U2W 273.It 274Adaptec 275.Tn 2950U2B 276.It 277Adaptec 278.Tn 19160B 279.It 280Adaptec 281.Tn 29160B 282.It 283Adaptec 284.Tn 29160N 285.It 286Adaptec 287.Tn 3940 288.It 289Adaptec 290.Tn 3940U 291.It 292Adaptec 293.Tn 3940AU 294.It 295Adaptec 296.Tn 3940UW 297.It 298Adaptec 299.Tn 3940AUW 300.It 301Adaptec 302.Tn 3940U2W 303.It 304Adaptec 305.Tn 3950U2 306.It 307Adaptec 308.Tn 3960 309.It 310Adaptec 311.Tn 39160 312.It 313Adaptec 314.Tn 3985 315.It 316Adaptec 317.Tn 4944UW 318.It 319Many motherboards with on-board 320.Tn SCSI 321support 322.El 323.Sh SCSI CONTROL BLOCKS (SCBs) 324Every transaction sent to a device on the SCSI bus is assigned a 325.Sq SCSI Control Block 326(SCB). 327The SCB contains all of the information required by the 328controller to process a transaction. 329The chip feature table lists 330the number of SCBs that can be stored in on-chip memory. 331All chips 332with model numbers greater than or equal to 7870 allow for the on chip 333SCB space to be augmented with external SRAM up to a maximum of 255 SCBs. 334Very few Adaptec controller configurations have external SRAM. 335.Pp 336If external SRAM is not available, SCBs are a limited resource. 337Using the SCBs in a straight forward manner would only allow the driver to 338handle as many concurrent transactions as there are physical SCBs. 339To fully utilize the SCSI bus and the devices on it, 340requires much more concurrency. 341The solution to this problem is 342.Em SCB Paging , 343a concept similar to memory paging. 344SCB paging takes advantage of 345the fact that devices usually disconnect from the SCSI bus for long 346periods of time without talking to the controller. 347The SCBs for disconnected transactions are only of use to the controller 348when the transfer is resumed. 349When the host queues another transaction 350for the controller to execute, the controller firmware will use a 351free SCB if one is available. 352Otherwise, the state of the most recently 353disconnected (and therefore most likely to stay disconnected) SCB is 354saved, via dma, to host memory, and the local SCB reused to start 355the new transaction. 356This allows the controller to queue up to 357255 transactions regardless of the amount of SCB space. 358Since the 359local SCB space serves as a cache for disconnected transactions, the 360more SCB space available, the less host bus traffic consumed saving 361and restoring SCB data. 362.Sh SEE ALSO 363.Xr ahd 4 , 364.Xr cd 4 , 365.Xr da 4 , 366.Xr sa 4 , 367.Xr scsi 4 368.Sh HISTORY 369The 370.Nm 371driver appeared in 372.Fx 2.0 . 373.Sh AUTHORS 374The 375.Nm 376driver, the 377.Tn AIC7xxx 378sequencer-code assembler, 379and the firmware running on the aic7xxx chips was written by 380.An Justin T. Gibbs . 381.Sh BUGS 382Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 383.Tn AIC7870 384Rev B in synchronous mode at 10MHz. 385Controllers with this problem have a 38642 MHz clock crystal on them and run slightly above 10MHz. 387This confuses the drive and hangs the bus. 388Setting a maximum synchronous negotiation rate of 8MHz in the 389.Tn SCSI-Select 390utility will allow normal operation. 391.Pp 392Although the Ultra2 and Ultra160 products have sufficient instruction 393ram space to support both the initiator and target roles concurrently, 394this configuration is disabled in favor of allowing the target role 395to respond on multiple target ids. 396A method for configuring dual role mode should be provided. 397.Pp 398Tagged Queuing is not supported in target mode. 399.Pp 400Reselection in target mode fails to function correctly on all high 401voltage differential boards as shipped by Adaptec. 402Information on 403how to modify HVD board to work correctly in target mode is available 404from Adaptec. 405