1.\" 2.\" Copyright (c) 1995, 1996, 1997 3.\" Justin T. Gibbs. All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 3. The name of the author may not be used to endorse or promote products 14.\" derived from this software withough specific prior written permission. 15.\" 16.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26.\" 27.\" $Id$ 28.\" 29.Dd April 20, 1996 30.Dt AHC 4 i386 31.Os FreeBSD 32.Sh NAME 33.Nm ahc 34.Nd Adaptec VL/EISA/PCI SCSI host adapter driver 35.Sh SYNOPSIS 36For one or more VL/EISA cards: 37.Cd controller eisa0 38.Cd controller ahc0 39.Pp 40For one or more PCI cards: 41.Cd controller pci0 42.Cd controller ahc0 43.Pp 44To enable SCB paging: 45.Cd options AHC_SCBPAGING_ENABLE 46.Pp 47To enable tagged queueing: 48.Cd options AHC_TAGENABLE 49.Pp 50To allow PCI adapters to use memory mapped I/O if enabled: 51.Cd options AHC_ALLOW_MEMIO 52.Pp 53For one or more SCSI busses: 54.Cd controller scbus0 at ahc0 55.Sh DESCRIPTION 56This driver provides access to the 57.Tn SCSI 58bus(es) connected to Adaptec 59274x, 284x, 2940, 3940, or controllers based on the 60.Tn AIC7770, 61.Tn AIC7850, 62.Tn AIC7860, 63.Tn AIC7870, 64or 65.Tn AIC7880 66host adapter chips. 67Features include support for twin and wide busses, 68ultra 69.Tn SCSI, 70two active commands at a time per non-tagged queueing target, 71tagged queuing, 72and SCB paging. 73.Pp 74The number of concurrent transactions allowed is chip dependent 75and ranges from 3 to 16. 76On PCI adapters, 77this number can be increased with the SCB paging option. 78SCB paging implements an algorithm to 'page-out' transactions 79that are in the disconnected state so that the freed space in 80the controller's memory can be used to start additional transactions. 81On the aic7880 and aic7870, 82this increases the maximum number of outstanding transactions from 16 to 255. 83On the aic7850 and aic7860 controllers, this maximum rises from 3 to 8. 84During the hardware probe, 85a diagnostic showing the ratio of hardware supported 'slots' to number 86of transactions is printed. 87SCB paging is enabled with the 88.Dq Dv AHC_SCBPAGING_ENABLE 89configuration option. 90This option will likely be removed and become the default behavior for 91adapters that support it, 92in the near future. 93.Pp 94Tagged queueing is enabled with the 95.Dq Dv AHC_TAGENABLE 96configuration option. 97Tagged queueing allows multiple transactions to be queued at the device 98level instead of the host level, 99allowing the device to re-order I/O to minimize seeks, 100seek distance, 101and to increase throughput. 102Tagged queueing can have a significant impact on performance for seek 103bound applications and should be enabled for most configurations. 104Unfortunantly, some devices that claim to support tagged queueing fail 105miserable when it is used. 106The only reason tagged queueing remains as a controller option is as a 107stop gap measure until a mechanism to detect these broken devices and to 108control this feature on a per device basis is in place. 109.Pp 110Memory mapped I/O can be enabled with the 111.Dq Dv AHC_ALLOW_MEMIO 112configuration option. 113Memory mapped I/O is more efficient than the alternative, programmed I/O. 114Most PCI BIOSes will map devices so that either technique for communicating 115with the card is availible. 116In some cases, 117usually when the PCI device is sitting behind a PCI->PCI bridge, 118the BIOS fails to properly initialize the chip for memory mapped I/O. 119The symptom of this problem is usually a system hang if memory mapped I/O 120is attempted. 121Most modern motherboards perform the initialization correctly and work fine 122with this option enabled. 123.Pp 124Per target configuration performed in the 125.Tn SCSI-Select 126menu, accesible at boot 127in 128.No non- Ns Tn EISA 129models, 130or through an 131.Tn EISA 132configuration utility for 133.Tn EISA 134models, 135is honored by this driver with the stipulation that the 136.Tn BIOS 137must be enabled for 138.Tn EISA 139adaptors. This includes synchronous/asynchronous transfers, 140maximum synchronous negotiation rate, 141disconnection, 142and the host adapter's SCSI ID. 143.Pp 144Note that I/O addresses are determined automatically by the probe routines, 145but care should be taken when using a 284x 146.Pq Tn VESA No local bus controller 147in an 148.Tn EISA 149system. Ensure that the jumpers setting the I/O area for the 284x match the 150.Tn EISA 151slot into which the card is inserted to prevent conflicts with other 152.Tn EISA 153cards. 154.Sh BUGS 155Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 156.Tn AIC7870 157Rev B in synchronous mode at 10MHz. Controllers with this problem have a 15842 MHz clock crystal on them and run slightly above 10MHz. This causes the 159drive much confusion. Setting a maximum synchronous negotiation rate of 8MHz 160in the 161.Tn SCSI-Select 162utility 163will allow normal function. 164.Sh SEE ALSO 165.Xr aha 4 , 166.Xr ahb 4 , 167.Xr cd 4 , 168.Xr scsi 4 , 169.Xr sd 4 , 170.Xr st 4 171.Sh AUTHOR 172The 173.Nm 174driver was written by Justin Gibbs. The 175.Tn AIC7xxx 176sequencer-code assembler was 177written by John Aycock. 178.Sh HISTORY 179The 180.Nm 181driver appeared in 182.Fx 2.1 . 183