1.\" 2.\" Copyright (c) 1995, 1996, 1997, 1998, 2000 3.\" Justin T. Gibbs. All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 3. The name of the author may not be used to endorse or promote products 14.\" derived from this software without specific prior written permission. 15.\" 16.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd February 13, 2000 30.Dt AHC 4 31.Os 32.Sh NAME 33.Nm ahc 34.Nd Adaptec VL/EISA/PCI SCSI host adapter driver 35.Sh SYNOPSIS 36For one or more VL/EISA cards: 37.Cd device eisa 38.Cd device ahc 39.Pp 40For one or more PCI cards: 41.Cd device pci 42.Cd device ahc 43.Pp 44To allow PCI adapters to use memory mapped I/O if enabled: 45.Cd options AHC_ALLOW_MEMIO 46.Pp 47To configure one or more controllers to assume the target role: 48.Cd options AHC_TMODE_ENABLE <bitmask of units> 49.Pp 50For one or more SCSI busses: 51.Cd device scbus 52.Sh DESCRIPTION 53This driver provides access to the 54.Tn SCSI 55bus(es) connected to Adaptec 56.Tn AIC7770 , 57.Tn AIC7850 , 58.Tn AIC7860 , 59.Tn AIC7870 , 60.Tn AIC7880 , 61.Tn AIC7890 , 62.Tn AIC7891 , 63.Tn AIC7892 , 64.Tn AIC7895 , 65.Tn AIC7896 , 66.Tn AIC7897 67and 68.Tn AIC7899 69host adapter chips. 70These chips are found on many motherboards as well as the following 71Adaptec SCSI controller cards: 72.Tn 274X(W) , 73.Tn 274X(T) , 74.Tn 284X , 75.Tn 2910 , 76.Tn 2915 , 77.Tn 2920 , 78.Tn 2930C , 79.Tn 2930U2 , 80.Tn 2940 , 81.Tn 2940U , 82.Tn 2940AU , 83.Tn 2940UW , 84.Tn 2940UW Dual , 85.Tn 2940UW Pro , 86.Tn 2940U2W , 87.Tn 2940U2B , 88.Tn 2950U2W , 89.Tn 2950U2B , 90.Tn 19160B , 91.Tn 29160B , 92.Tn 29160N , 93.Tn 3940 , 94.Tn 3940U , 95.Tn 3940AU , 96.Tn 3940UW , 97.Tn 3940AUW , 98.Tn 3940U2W , 99.Tn 3950U2 , 100.Tn 3960 , 101.Tn 39160 , 102.Tn 3985 , 103and 104.Tn 4944UW . 105.Pp 106Driver features include support for twin and wide busses, 107fast, ultra or ultra2 synchronous transfers depending on controller type, 108tagged queueing, SCB paging, and target mode. 109.Pp 110Memory mapped I/O can be enabled for PCI devices with the 111.Dq Dv AHC_ALLOW_MEMIO 112configuration option. 113Memory mapped I/O is more efficient than the alternative, programmed I/O. 114Most PCI BIOSes will map devices so that either technique for communicating 115with the card is available. 116In some cases, 117usually when the PCI device is sitting behind a PCI->PCI bridge, 118the BIOS may fail to properly initialize the chip for memory mapped I/O. 119The typical symptom of this problem is a system hang if memory mapped I/O 120is attempted. 121Most modern motherboards perform the initialization correctly and work fine 122with this option enabled. 123.Pp 124Individual controllers may be configured to operate in the target role 125through the 126.Dq Dv AHC_TMODE_ENABLE 127configuration option. The value assigned to this option should be a bitmap 128of all units where target mode is desired. 129For example, a value of 0x25, would enable target mode on units 0, 2, and 5. 130A value of 0x8a enables it for units 1, 3, and 7. 131.Pp 132Per target configuration performed in the 133.Tn SCSI-Select 134menu, accessible at boot 135in 136.No non- Ns Tn EISA 137models, 138or through an 139.Tn EISA 140configuration utility for 141.Tn EISA 142models, 143is honored by this driver. 144This includes synchronous/asynchronous transfers, 145maximum synchronous negotiation rate, 146wide transfers, 147disconnection, 148the host adapter's SCSI ID, 149and, 150in the case of 151.Tn EISA 152Twin Channel controllers, 153the primary channel selection. 154For systems that store non-volatile settings in a system specific manner 155rather than a serial eeprom directly connected to the aic7xxx controller, 156the 157.Tn BIOS 158must be enabled for the driver to access this information. 159This restriction applies to all 160.Tn EISA 161and many motherboard configurations. 162.Pp 163Note that I/O addresses are determined automatically by the probe routines, 164but care should be taken when using a 284x 165.Pq Tn VESA No local bus controller 166in an 167.Tn EISA 168system. The jumpers setting the I/O area for the 284x should match the 169.Tn EISA 170slot into which the card is inserted to prevent conflicts with other 171.Tn EISA 172cards. 173.Pp 174Performance and feature sets vary throughout the aic7xxx product line. 175The following table provides a comparison of the different chips supported 176by the 177.Nm 178driver. Note that wide and twin channel features, although always supported 179by a particular chip, may be disabled in a particular motherboard or card 180design. 181.Pp 182.Bd -ragged -offset indent 183.Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features 184.Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features" 185aic7770 10 EISA/VL 10MHz 16Bit 4 1 186aic7850 10 PCI/32 10MHz 8Bit 3 187aic7860 10 PCI/32 20MHz 8Bit 3 188aic7870 10 PCI/32 10MHz 16Bit 16 189aic7880 10 PCI/32 20MHz 16Bit 16 190aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8 191aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8 192aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8 193aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 194aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8 195aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8 196aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8 197aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8 198.El 199.Pp 200.Bl -enum -compact 201.It 202Multiplexed Twin Channel Device - One controller servicing two busses. 203.It 204Multi-function Twin Channel Device - Two controllers on one chip. 205.It 206Command Channel Secondary DMA Engine - Allows scatter gather list and 207SCB prefetch. 208.It 20964 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA. 210.It 211Block Move Instruction Support - Doubles the speed of certain sequencer 212operations. 213.It 214.Sq Bayonet 215style Scatter Gather Engine - Improves S/G prefetch performance. 216.It 217Queuing Registers - Allows queueing of new transactions without pausing the 218sequencer. 219.It 220Multiple Target IDs - Allows the controller to respond to selection as a 221target on multiple SCSI IDs. 222.El 223.Ed 224.Sh SCSI CONTROL BLOCKS (SCBs) 225Every transaction sent to a device on the SCSI bus is assigned a 226.Sq SCSI Control Block 227(SCB). The SCB contains all of the information required by the 228controller to process a transaction. The chip feature table lists 229the number of SCBs that can be stored in on-chip memory. All chips 230with model numbers greater than or equal to 7870 allow for the on chip 231SCB space to be augmented with external SRAM up to a maximum of 255 SCBs. 232Very few Adaptec controller configurations have external SRAM. 233.Pp 234If external SRAM is not available, SCBs are a limited resource. 235Using the SCBs in a straight forward manner would only allow the driver to 236handle as many concurrent transactions as there are physical SCBs. 237To fully utilize the SCSI bus and the devices on it, 238requires much more concurrency. 239The solution to this problem is 240.Em SCB Paging , 241a concept similar to memory paging. SCB paging takes advantage of 242the fact that devices usually disconnect from the SCSI bus for long 243periods of time without talking to the controller. The SCBs 244for disconnected transactions are only of use to the controller 245when the transfer is resumed. When the host queues another transaction 246for the controller to execute, the controller firmware will use a 247free SCB if one is available. Otherwise, the state of the most recently 248disconnected (and therefore most likely to stay disconnected) SCB is 249saved, via dma, to host memory, and the local SCB reused to start 250the new transaction. This allows the controller to queue up to 251255 transactions regardless of the amount of SCB space. Since the 252local SCB space serves as a cache for disconnected transactions, the 253more SCB space available, the less host bus traffic consumed saving 254and restoring SCB data. 255.Sh BUGS 256Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 257.Tn AIC7870 258Rev B in synchronous mode at 10MHz. Controllers with this problem have a 25942 MHz clock crystal on them and run slightly above 10MHz. This confuses 260the drive and hangs the bus. Setting a maximum synchronous negotiation rate 261of 8MHz in the 262.Tn SCSI-Select 263utility will allow normal operation. 264.Pp 265Although the Ultra2 and Ultra160 products have sufficient instruction 266ram space to support both the initiator and target roles concurrently, 267this configuration is disabled in favor of allowing the target role 268to respond on multiple target ids. A method for configuring dual 269role mode should be provided. 270.Pp 271Tagged Queuing is not supported in target mode. 272.Pp 273Reselection in target mode fails to function correctly on all high 274voltage differential boards as shipped by Adaptec. Information on 275how to modify HVD board to work correctly in target mode is available 276from Adaptec. 277.Sh SEE ALSO 278.Xr aha 4 , 279.Xr ahb 4 , 280.Xr cd 4 , 281.Xr da 4 , 282.Xr sa 4 , 283.Xr scsi 4 284.Sh AUTHORS 285The 286.Nm 287driver, the 288.Tn AIC7xxx 289sequencer-code assembler, 290and the firmware running on the aic7xxx chips was written by 291.An Justin T. Gibbs . 292.Sh HISTORY 293The 294.Nm 295driver appeared in 296.Fx 2.0 . 297