1.\" 2.\" Copyright (c) 1995, 1996, 1997, 1998, 2000 3.\" Justin T. Gibbs. All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 3. The name of the author may not be used to endorse or promote products 14.\" derived from this software without specific prior written permission. 15.\" 16.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd February 13, 2000 30.Dt AHC 4 31.Os 32.Sh NAME 33.Nm ahc 34.Nd Adaptec VL/EISA/PCI SCSI host adapter driver 35.Sh SYNOPSIS 36For one or more VL/EISA cards: 37.Cd device eisa 38.Cd device ahc 39.Pp 40For one or more PCI cards: 41.Cd device pci 42.Cd device ahc 43.Pp 44To allow PCI adapters to use memory mapped I/O if enabled: 45.Cd options AHC_ALLOW_MEMIO 46.Pp 47To configure one or more controllers to assume the target role: 48.Cd options AHC_TMODE_ENABLE <bitmask of units> 49.Pp 50For one or more SCSI busses: 51.Cd device scbus 52.Sh DESCRIPTION 53This driver provides access to the 54.Tn SCSI 55bus(es) connected to Adaptec 56.Tn AIC7770 , 57.Tn AIC7850 , 58.Tn AIC7860 , 59.Tn AIC7870 , 60.Tn AIC7880 , 61.Tn AIC7890 , 62.Tn AIC7891 , 63.Tn AIC7892 , 64.Tn AIC7895 , 65.Tn AIC7896 , 66.Tn AIC7897 67and 68.Tn AIC7899 69host adapter chips. 70These chips are found on many motherboards as well as the following 71Adaptec SCSI controller cards: 72.Tn 274X(W) , 73.Tn 274X(T) , 74.Tn 284X , 75.Tn 2910 , 76.Tn 2915 , 77.Tn 2920 , 78.Tn 2930C , 79.Tn 2930U2 , 80.Tn 2940 , 81.Tn 2940U , 82.Tn 2940AU , 83.Tn 2940UW , 84.Tn 2940UW Dual , 85.Tn 2940UW Pro , 86.Tn 2940U2W , 87.Tn 2940U2B , 88.Tn 2950U2W , 89.Tn 2950U2B , 90.Tn 19160B , 91.Tn 29160B , 92.Tn 29160N , 93.Tn 3940 , 94.Tn 3940U , 95.Tn 3940AU , 96.Tn 3940UW , 97.Tn 3940AUW , 98.Tn 3940U2W , 99.Tn 3950U2 , 100.Tn 3960 , 101.Tn 39160 , 102.Tn 3985 , 103and 104.Tn 4944UW . 105.Pp 106Driver features include support for twin and wide busses, 107fast, ultra or ultra2 synchronous transfers depending on controller type, 108tagged queueing, SCB paging, and target mode. 109.Pp 110Memory mapped I/O can be enabled for PCI devices with the 111.Dq Dv AHC_ALLOW_MEMIO 112configuration option. 113Memory mapped I/O is more efficient than the alternative, programmed I/O. 114Most PCI BIOSes will map devices so that either technique for communicating 115with the card is available. 116In some cases, 117usually when the PCI device is sitting behind a PCI->PCI bridge, 118the BIOS may fail to properly initialize the chip for memory mapped I/O. 119The typical symptom of this problem is a system hang if memory mapped I/O 120is attempted. 121Most modern motherboards perform the initialization correctly and work fine 122with this option enabled. 123.Pp 124Individual controllers may be configured to operate in the target role 125through the 126.Dq Dv AHC_TMODE_ENABLE 127configuration option. The value assigned to this option should be a bitmap 128of all units where target mode is desired. 129For example, a value of 0x25, would enable target mode on units 0, 2, and 5. 130.Pp 131Per target configuration performed in the 132.Tn SCSI-Select 133menu, accessible at boot 134in 135.No non- Ns Tn EISA 136models, 137or through an 138.Tn EISA 139configuration utility for 140.Tn EISA 141models, 142is honored by this driver. 143This includes synchronous/asynchronous transfers, 144maximum synchronous negotiation rate, 145wide transfers, 146disconnection, 147the host adapter's SCSI ID, 148and, 149in the case of 150.Tn EISA 151Twin Channel controllers, 152the primary channel selection. 153For systems that store non-volatile settings in a system specific manner 154rather than a serial eeprom directly connected to the aic7xxx controller, 155the 156.Tn BIOS 157must be enabled for the driver to access this information. 158This restriction applies to all 159.Tn EISA 160and many motherboard configurations. 161.Pp 162Note that I/O addresses are determined automatically by the probe routines, 163but care should be taken when using a 284x 164.Pq Tn VESA No local bus controller 165in an 166.Tn EISA 167system. The jumpers setting the I/O area for the 284x should match the 168.Tn EISA 169slot into which the card is inserted to prevent conflicts with other 170.Tn EISA 171cards. 172.Pp 173Performance and feature sets vary throughout the aic7xxx product line. 174The following table provides a comparison of the different chips supported 175by the 176.Nm 177driver. Note that wide and twin channel features, although always supported 178by a particular chip, may be disabled in a particular motherboard or card 179design. 180.Pp 181.Bd -ragged -offset indent 182.Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features 183.Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features" 184aic7770 10 EISA/VL 10MHz 16Bit 4 1 185aic7850 10 PCI/32 10MHz 8Bit 3 186aic7860 10 PCI/32 20MHz 8Bit 3 187aic7870 10 PCI/32 10MHz 16Bit 16 188aic7880 10 PCI/32 20MHz 16Bit 16 189aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8 190aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8 191aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8 192aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 193aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8 194aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8 195aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8 196aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8 197.El 198.Pp 199.Bl -enum -compact 200.It 201Multiplexed Twin Channel Device - One controller servicing two busses. 202.It 203Multi-function Twin Channel Device - Two controllers on one chip. 204.It 205Command Channel Secondary DMA Engine - Allows scatter gather list and 206SCB prefetch. 207.It 20864 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA. 209.It 210Block Move Instruction Support - Doubles the speed of certain sequencer 211operations. 212.It 213.Sq Bayonet 214style Scatter Gather Engine - Improves S/G prefetch performance. 215.It 216Queuing Registers - Allows queueing of new transactions without pausing the 217sequencer. 218.It 219Multiple Target IDs - Allows the controller to respond to selection as a 220target on multiple SCSI IDs. 221.El 222.Ed 223.Sh SCSI CONTROL BLOCKS (SCBs) 224Every transaction sent to a device on the SCSI bus is assigned a 225.Sq SCSI Control Block 226(SCB). The SCB contains all of the information required by the 227controller to process a transaction. The chip feature table lists 228the number of SCBs that can be stored in on-chip memory. All chips 229with model numbers greater than or equal to 7870 allow for the on chip 230SCB space to be augmented with external SRAM up to a maximum of 255 SCBs. 231Very few Adaptec controller configurations have external SRAM. 232.Pp 233If external SRAM is not available, SCBs are a limited resource. 234Using the SCBs in a straight forward manner would only allow the driver to 235handle as many concurrent transactions as there are physical SCBs. 236To fully utilize the SCSI bus and the devices on it, 237requires much more concurrency. 238The solution to this problem is 239.Em SCB Paging , 240a concept similar to memory paging. SCB paging takes advantage of 241the fact that devices usually disconnect from the SCSI bus for long 242periods of time without talking to the controller. The SCBs 243for disconnected transactions are only of use to the controller 244when the transfer is resumed. When the host queues another transaction 245for the controller to execute, the controller firmware will use a 246free SCB if one is available. Otherwise, the state of the most recently 247disconnected (and therefore most likely to stay disconnected) SCB is 248saved, via dma, to host memory, and the local SCB reused to start 249the new transaction. This allows the controller to queue up to 250255 transactions regardless of the amount of SCB space. Since the 251local SCB space serves as a cache for disconnected transactions, the 252more SCB space available, the less host bus traffic consumed saving 253and restoring SCB data. 254.Sh BUGS 255Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 256.Tn AIC7870 257Rev B in synchronous mode at 10MHz. Controllers with this problem have a 25842 MHz clock crystal on them and run slightly above 10MHz. This confuses 259the drive and hangs the bus. Setting a maximum synchronous negotiation rate 260of 8MHz in the 261.Tn SCSI-Select 262utility will allow normal operation. 263.Pp 264Although the Ultra2 and Ultra160 products have sufficient instruction 265ram space to support both the initiator and target roles concurrently, 266this configuration is disabled in favor of allowing the target role 267to respond on multiple target ids. A method for configuring dual 268role mode should be provided. 269.Pp 270Tagged Queuing is not supported in target mode. 271.Pp 272Reselection in target mode fails to function correctly on all high 273voltage differential boards as shipped by Adaptec. Information on 274how to modify HVD board to work correctly in target mode is available 275from Adaptec. 276.Sh SEE ALSO 277.Xr aha 4 , 278.Xr ahb 4 , 279.Xr cd 4 , 280.Xr da 4 , 281.Xr sa 4 , 282.Xr scsi 4 283.Sh AUTHORS 284The 285.Nm 286driver, the 287.Tn AIC7xxx 288sequencer-code assembler, 289and the firmware running on the aic7xxx chips was written by 290.An Justin T. Gibbs . 291.Sh HISTORY 292The 293.Nm 294driver appeared in 295.Fx 2.0 . 296