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27.Dd February 15, 2017
28.Dt AHC 4
29.Os
30.Sh NAME
31.Nm ahc
32.Nd Adaptec VL/ISA/PCI SCSI host adapter driver
33.Sh SYNOPSIS
34To compile this driver into the kernel,
35place the following lines in your
36kernel configuration file:
37.Bd -ragged -offset indent
38.Cd "device scbus"
39.Cd "device ahc"
40.Pp
41For one or more PCI cards:
42.Cd "device pci"
43.Ed
44.Pp
45Alternatively, to load the driver as a
46module at boot time, place the following lines in
47.Xr loader.conf 5 :
48.Bd -literal -offset indent
49ahc_load="YES"
50ahc_isa_load="YES"
51ahc_pci_load="YES"
52.Ed
53.Sh DESCRIPTION
54This driver provides access to the
55.Tn SCSI
56bus(es) connected to the Adaptec AIC77xx and AIC78xx
57host adapter chips.
58.Pp
59Driver features include support for twin and wide busses,
60fast, ultra or ultra2 synchronous transfers depending on controller type,
61tagged queueing, SCB paging, and target mode.
62.Pp
63Per target configuration performed in the
64.Tn SCSI-Select
65menu, accessible at boot
66is honored by this driver.
67This includes synchronous/asynchronous transfers,
68maximum synchronous negotiation rate,
69wide transfers,
70disconnection,
71the host adapter's SCSI ID.
72For systems that store non-volatile settings in a system specific manner
73rather than a serial eeprom directly connected to the aic7xxx controller,
74the
75.Tn BIOS
76must be enabled for the driver to access this information.
77This restriction applies to
78many chip-down motherboard configurations.
79.Pp
80Performance and feature sets vary throughout the aic7xxx product line.
81The following table provides a comparison of the different chips supported
82by the
83.Nm
84driver.
85Note that wide and twin channel features, although always supported
86by a particular chip, may be disabled in a particular motherboard or card
87design.
88.Bd -ragged -offset indent
89.Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
90.It Em "Chip" Ta "MIPS" Ta "Bus" Ta "MaxSync" Ta "MaxWidth" Ta "SCBs" Ta "Features"
91.It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
92.It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
93.It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
94.It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
95.It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
96.It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
97.It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
98.It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
99.It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5"
100.It "aic7895C" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 8"
101.It "aic7896" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
102.It "aic7897" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
103.It "aic7899" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
104.El
105.Pp
106.Bl -enum -compact
107.It
108Multiplexed Twin Channel Device - One controller servicing two busses.
109.It
110Multi-function Twin Channel Device - Two controllers on one chip.
111.It
112Command Channel Secondary DMA Engine - Allows scatter gather list and
113SCB prefetch.
114.It
11564 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
116.It
117Block Move Instruction Support - Doubles the speed of certain sequencer
118operations.
119.It
120.Sq Bayonet
121style Scatter Gather Engine - Improves S/G prefetch performance.
122.It
123Queuing Registers - Allows queueing of new transactions without pausing the
124sequencer.
125.It
126Multiple Target IDs - Allows the controller to respond to selection as a
127target on multiple SCSI IDs.
128.El
129.Ed
130.Sh CONFIGURATION OPTIONS
131.Pp
132To allow PCI adapters to use memory mapped I/O if enabled:
133.Pp
134.Cd options AHC_ALLOW_MEMIO=(0 -- disabled, 1 -- enabled)
135.Bd -ragged -offset indent
136Memory mapped I/O is more efficient than the alternative, programmed I/O.
137Most PCI BIOSes will map devices so that either technique for communicating
138with the card is available.  In some cases, usually when the PCI device is
139sitting behind a PCI->PCI bridge, the BIOS may fail to properly initialize
140the chip for memory mapped I/O. The typical symptom of this problem is a
141system hang if memory mapped I/O is attempted.
142.Pp
143Most modern motherboards perform the initialization correctly and work fine
144with this option enabled and it is the default. This option can also be
145dynamically configued through a device hint documented below.
146.Ed
147.Pp
148To statically configure one or more controllers to assume the target role:
149.Pp
150.Cd options AHC_TMODE_ENABLE=<bitmask of units>
151.Bd -ragged -offset indent
152The value assigned to this option should be a bitmap of all units where target
153mode is desired. For example, a value of 0x25, would enable target mode on
154units 0, 2, and 5. A value of 0x8a enables it for units 1, 3, and 7.
155.Pp
156Note that controllers can be dynamically configured through a device hint
157documented below.
158.El
159.Ed
160.Sh BOOT OPTIONS
161The following options are switchable by setting values in
162.Pa /boot/device.hints .
163.Pp
164They are:
165.Bl -tag -width indent
166.It Va hint.ahc. Ns Ar N Ns Va .tmode_enable
167A hint to define whether the SCSI target mode is enabled, defaults to disabled
168(0 -- disabled, 1 -- enabled).
169.It Va hint.ahc. Ns Ar N Ns Va .allow_memio
170A hint to define whether memory mapped io is enabled or disabled for this
171adapter, defaults to enabled (0 -- disabled, 1 -- enabled).
172.El
173.Sh HARDWARE
174The
175.Nm
176driver supports the following
177.Tn SCSI
178host adapter chips and
179.Tn SCSI
180controller cards:
181.Pp
182.Bl -bullet -compact
183.It
184Adaptec
185.Tn AIC7770
186host adapter chip
187.It
188Adaptec
189.Tn AIC7850
190host adapter chip
191.It
192Adaptec
193.Tn AIC7860
194host adapter chip
195.It
196Adaptec
197.Tn AIC7870
198host adapter chip
199.It
200Adaptec
201.Tn AIC7880
202host adapter chip
203.It
204Adaptec
205.Tn AIC7890
206host adapter chip
207.It
208Adaptec
209.Tn AIC7891
210host adapter chip
211.It
212Adaptec
213.Tn AIC7892
214host adapter chip
215.It
216Adaptec
217.Tn AIC7895
218host adapter chip
219.It
220Adaptec
221.Tn AIC7896
222host adapter chip
223.It
224Adaptec
225.Tn AIC7897
226host adapter chip
227.It
228Adaptec
229.Tn AIC7899
230host adapter chip
231.It
232Adaptec
233.Tn 274X(W)
234.It
235Adaptec
236.Tn 274X(T)
237.It
238Adaptec
239.Tn 2910
240.It
241Adaptec
242.Tn 2915
243.It
244Adaptec
245.Tn 2920C
246.It
247Adaptec
248.Tn 2930C
249.It
250Adaptec
251.Tn 2930U2
252.It
253Adaptec
254.Tn 2940
255.It
256Adaptec
257.Tn 2940J
258.It
259Adaptec
260.Tn 2940N
261.It
262Adaptec
263.Tn 2940U
264.It
265Adaptec
266.Tn 2940AU
267.It
268Adaptec
269.Tn 2940UW
270.It
271Adaptec
272.Tn 2940UW Dual
273.It
274Adaptec
275.Tn 2940UW Pro
276.It
277Adaptec
278.Tn 2940U2W
279.It
280Adaptec
281.Tn 2940U2B
282.It
283Adaptec
284.Tn 2950U2W
285.It
286Adaptec
287.Tn 2950U2B
288.It
289Adaptec
290.Tn 19160B
291.It
292Adaptec
293.Tn 29160B
294.It
295Adaptec
296.Tn 29160N
297.It
298Adaptec
299.Tn 3940
300.It
301Adaptec
302.Tn 3940U
303.It
304Adaptec
305.Tn 3940AU
306.It
307Adaptec
308.Tn 3940UW
309.It
310Adaptec
311.Tn 3940AUW
312.It
313Adaptec
314.Tn 3940U2W
315.It
316Adaptec
317.Tn 3950U2
318.It
319Adaptec
320.Tn 3960
321.It
322Adaptec
323.Tn 39160
324.It
325Adaptec
326.Tn 3985
327.It
328Adaptec
329.Tn 4944UW
330.It
331Many motherboards with on-board
332.Tn SCSI
333support
334.El
335.Sh SCSI CONTROL BLOCKS (SCBs)
336Every transaction sent to a device on the SCSI bus is assigned a
337.Sq SCSI Control Block
338(SCB).
339The SCB contains all of the information required by the
340controller to process a transaction.
341The chip feature table lists
342the number of SCBs that can be stored in on-chip memory.
343All chips
344with model numbers greater than or equal to 7870 allow for the on chip
345SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
346Very few Adaptec controller configurations have external SRAM.
347.Pp
348If external SRAM is not available, SCBs are a limited resource.
349Using the SCBs in a straight forward manner would only allow the driver to
350handle as many concurrent transactions as there are physical SCBs.
351To fully utilize the SCSI bus and the devices on it,
352requires much more concurrency.
353The solution to this problem is
354.Em SCB Paging ,
355a concept similar to memory paging.
356SCB paging takes advantage of
357the fact that devices usually disconnect from the SCSI bus for long
358periods of time without talking to the controller.
359The SCBs for disconnected transactions are only of use to the controller
360when the transfer is resumed.
361When the host queues another transaction
362for the controller to execute, the controller firmware will use a
363free SCB if one is available.
364Otherwise, the state of the most recently
365disconnected (and therefore most likely to stay disconnected) SCB is
366saved, via dma, to host memory, and the local SCB reused to start
367the new transaction.
368This allows the controller to queue up to
369255 transactions regardless of the amount of SCB space.
370Since the
371local SCB space serves as a cache for disconnected transactions, the
372more SCB space available, the less host bus traffic consumed saving
373and restoring SCB data.
374.Sh SEE ALSO
375.Xr ahd 4 ,
376.Xr cd 4 ,
377.Xr da 4 ,
378.Xr sa 4 ,
379.Xr scsi 4
380.Sh HISTORY
381The
382.Nm
383driver appeared in
384.Fx 2.0 .
385.Sh AUTHORS
386The
387.Nm
388driver, the
389.Tn AIC7xxx
390sequencer-code assembler,
391and the firmware running on the aic7xxx chips was written by
392.An Justin T. Gibbs .
393.Sh BUGS
394Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
395.Tn AIC7870
396Rev B in synchronous mode at 10MHz.
397Controllers with this problem have a
39842 MHz clock crystal on them and run slightly above 10MHz.
399This confuses the drive and hangs the bus.
400Setting a maximum synchronous negotiation rate of 8MHz in the
401.Tn SCSI-Select
402utility will allow normal operation.
403.Pp
404Although the Ultra2 and Ultra160 products have sufficient instruction
405ram space to support both the initiator and target roles concurrently,
406this configuration is disabled in favor of allowing the target role
407to respond on multiple target ids.
408A method for configuring dual role mode should be provided.
409.Pp
410Tagged Queuing is not supported in target mode.
411.Pp
412Reselection in target mode fails to function correctly on all high
413voltage differential boards as shipped by Adaptec.
414Information on
415how to modify HVD board to work correctly in target mode is available
416from Adaptec.
417