1.\" 2.\" Copyright (c) 1995, 1996, 1997, 1998 3.\" Justin T. Gibbs. All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 3. The name of the author may not be used to endorse or promote products 14.\" derived from this software without specific prior written permission. 15.\" 16.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26.\" 27.\" $FreeBSD$ 28.\" 29.Dd October 15, 1998 30.Dt AHC 4 i386 31.Os FreeBSD 32.Sh NAME 33.Nm ahc 34.Nd Adaptec VL/EISA/PCI SCSI host adapter driver 35.Sh SYNOPSIS 36For one or more VL/EISA cards: 37.Cd controller eisa0 38.Cd controller ahc0 39.Pp 40For one or more PCI cards: 41.Cd controller pci0 42.Cd controller ahc0 43.Pp 44To allow PCI adapters to use memory mapped I/O if enabled: 45.Cd options AHC_ALLOW_MEMIO 46.Pp 47For one or more SCSI busses: 48.Cd controller scbus0 at ahc0 49.Sh DESCRIPTION 50This driver provides access to the 51.Tn SCSI 52bus(es) connected to Adaptec 53.Tn AIC7770, 54.Tn AIC7850, 55.Tn AIC7860, 56.Tn AIC7870, 57.Tn AIC7880, 58.Tn AIC7890, 59.Tn AIC7891, 60.Tn AIC7895, 61.Tn AIC7896, 62or 63.Tn AIC7897 64host adapter chips. 65These chips are found on many motherboards as well as the following 66Adaptec SCSI controller cards: 67.Tn 274X(W), 68.Tn 274X(T), 69.Tn 284X, 70.Tn 2920C, 71.Tn 2930U2, 72.Tn 2940, 73.Tn 2940U, 74.Tn 2940AU, 75.Tn 2940UW, 76.Tn 2940UW Dual, 77.Tn 2940U2W, 78.Tn 2940U2B, 79.Tn 2950U2W, 80.Tn 2950U2B, 81.Tn 3940, 82.Tn 3940U, 83.Tn 3940AU, 84.Tn 3940UW, 85.Tn 3940AUW, 86.Tn 3940U2W, 87.Tn 3950U2, 88and 89.Tn 3985. 90.Pp 91Driver features include support for twin and wide busses, 92fast, ultra and ultra2 synchronous transfers depending on controller type, 93tagged queuing, 94and SCB paging. 95.Pp 96Memory mapped I/O can be enabled for PCI devices with the 97.Dq Dv AHC_ALLOW_MEMIO 98configuration option. 99Memory mapped I/O is more efficient than the alternative, programmed I/O. 100Most PCI BIOSes will map devices so that either technique for communicating 101with the card is available. 102In some cases, 103usually when the PCI device is sitting behind a PCI->PCI bridge, 104the BIOS fails to properly initialize the chip for memory mapped I/O. 105The symptom of this problem is usually a system hang if memory mapped I/O 106is attempted. 107Most modern motherboards perform the initialization correctly and work fine 108with this option enabled. 109.Pp 110Per target configuration performed in the 111.Tn SCSI-Select 112menu, accessible at boot 113in 114.No non- Ns Tn EISA 115models, 116or through an 117.Tn EISA 118configuration utility for 119.Tn EISA 120models, 121is honored by this driver with the stipulation that the 122.Tn BIOS 123must be enabled for 124.Tn EISA 125adaptors. This includes synchronous/asynchronous transfers, 126maximum synchronous negotiation rate, 127disconnection, 128the host adapter's SCSI ID, 129and, 130in the case of 131.Tn EISA 132Twin Channel controllers, 133the primary channel selection. 134.Pp 135Note that I/O addresses are determined automatically by the probe routines, 136but care should be taken when using a 284x 137.Pq Tn VESA No local bus controller 138in an 139.Tn EISA 140system. Ensure that the jumpers setting the I/O area for the 284x match the 141.Tn EISA 142slot into which the card is inserted to prevent conflicts with other 143.Tn EISA 144cards. 145.Pp 146Performance and feature sets vary throughout the aic7xxx product line. 147The following table provides a comparison of the different chips supported 148by the 149.Nm 150driver. Note that wide and twin channel features, although always supported 151by a particular chip, may be disabled in a particular motherboard or card 152design. 153.Pp 154.Bd -filled -offset indent 155.Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features 156.Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features" 157aic7770 10 EISA/VL 10MHz 16Bit 4 1 158aic7850 10 PCI/32 10MHz 8Bit 3 159aic7860 10 PCI/32 20MHz 8Bit 3 160aic7870 10 PCI/32 10MHz 16Bit 16 161aic7880 10 PCI/32 20MHz 16Bit 16 162aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 163aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 164aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 165aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 166aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 167.El 168.Pp 169.Bl -enum -compact 170.It 171Multiplexed Twin Channel Device - One controller servicing two busses. 172.It 173Multi-function Twin Channel Device - Two controllers on one chip. 174.It 175Command Channel Secondary DMA Engine - Allows scatter gather list and 176SCB prefetch. 177.It 17864 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA. 179.It 180Block Move Instruction Support - Doubles the speed of certain sequencer 181operations. 182.It 183.Sq Bayonet 184style Scatter Gather Engine - Improves S/G prefetch performance. 185.It 186Queuing Registers - Allows queuing of new transactions without pausing the 187sequencer. 188.El 189.Ed 190.Pp 191 192.Sh SCSI CONTROL BLOCKS (SCBs) 193Every transaction sent to a device on the SCSI bus is assigned a 194.Sq SCSI Control Block 195(SCB). The SCB contains all of the information required by the 196controller to process a transaction. The chip feature table lists 197the number of SCBs that can be stored in on chip memory. All chips 198with model numbers greater than or equal to 7870 allow for the on chip 199SCB space to be augmented with external SRAM up to a maximum of 255 SCBs. 200Very few Adaptec controller have external SRAM. 201 202If external SRAM is not available, SCBs are a limited resource and 203using them in a straight forward manner would only allow us to 204keep as many transactions as there are SCBs outstanding at a time. 205This would not allow enough concurrency to fully utilize the SCSI 206bus and it's devices. The solution to this problem is 207.Em SCB Paging , 208a concept similar to memory paging. SCB paging takes advantage of 209the fact that devices usually disconnect from the SCSI bus for long 210periods of time without talking to the controller. The SCBs 211for disconnected transactions are only of use to the controller 212when the transfer is resumed. When the host queues another transaction 213for the controller to execute, the controller firmware will use a 214free SCB if one is available. Otherwise, the state of the most recently 215disconnected (and therefor most likely to stay disconnected) SCB is 216saved, via dma, to host memory, and the local SCB reused to start 217the new transaction. This allows the controller to queue up to 218255 transactions regardless of the amount of SCB space. Since the 219local SCB space serves as a cache for disconnected transactions, the 220more SCB space available, the less host bus traffic consumed saving 221and restoring SCB data. 222.Sh BUGS 223Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 224.Tn AIC7870 225Rev B in synchronous mode at 10MHz. Controllers with this problem have a 22642 MHz clock crystal on them and run slightly above 10MHz. This confuses 227the drive and hangs the bus. Setting a maximum synchronous negotiation rate 228of 8MHz in the 229.Tn SCSI-Select 230utility 231will allow normal operation. 232.Sh SEE ALSO 233.Xr aha 4 , 234.Xr ahb 4 , 235.Xr cd 4 , 236.Xr da 4 , 237.Xr sa 4 , 238.Xr scsi 4 239.Sh AUTHORS 240The 241.Nm 242driver, the 243.Tn AIC7xxx 244sequencer-code assembler, 245and the firmware running on the aic7xxx chips was written by 246.An Justin T. Gibbs . 247.Sh HISTORY 248The 249.Nm 250driver appeared in 251.Fx 2.0 . 252