1.\" 2.\" Copyright (c) 1995, 1996, 1997, 1998 3.\" Justin T. Gibbs. All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 3. The name of the author may not be used to endorse or promote products 14.\" derived from this software withough specific prior written permission. 15.\" 16.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26.\" 27.\" $Id: ahc.4,v 1.12 1998/06/13 19:06:49 steve Exp $ 28.\" 29.Dd October 15, 1998 30.Dt AHC 4 i386 31.Os FreeBSD 32.Sh NAME 33.Nm ahc 34.Nd Adaptec VL/EISA/PCI SCSI host adapter driver 35.Sh SYNOPSIS 36For one or more VL/EISA cards: 37.Cd controller eisa0 38.Cd controller ahc0 39.Pp 40For one or more PCI cards: 41.Cd controller pci0 42.Cd controller ahc0 43.Pp 44To allow PCI adapters to use memory mapped I/O if enabled: 45.Cd options AHC_ALLOW_MEMIO 46.Pp 47For one or more SCSI busses: 48.Cd controller scbus0 at ahc0 49.Sh DESCRIPTION 50This driver provides access to the 51.Tn SCSI 52bus(es) connected to Adaptec 53.Tn AIC7770, 54.Tn AIC7850, 55.Tn AIC7860, 56.Tn AIC7870, 57.Tn AIC7880, 58.Tn AIC7890, 59.Tn AIC7891, 60.Tn AIC7895, 61.Tn AIC7896, 62or 63.Tn AIC7897 64host adapter chips. 65These chips are found on many motherboards as well as the following 66Adaptec SCSI controller cards: 67.Tn 274X(W), 68.Tn 274X(T), 69.Tn 284X, 70.Tn 2920C, 71.Tn 2940, 72.Tn 2940U, 73.Tn 2940AU, 74.Tn 2940UW, 75.Tn 2940UW Dual, 76.Tn 2940U2W, 77.Tn 2940U2B, 78.Tn 2950U2W, 79.Tn 2950U2B, 80.Tn 3940, 81.Tn 3940U, 82.Tn 3940AU, 83.Tn 3940UW, 84.Tn 3940AUW, 85.Tn 3940U2W, 86and 87.Tn 3985. 88.Pp 89Driver features include support for twin and wide busses, 90fast, ultra and ultra2 synchronous transfers depending on controller type, 91tagged queueing, 92and SCB paging. 93.Pp 94Memory mapped I/O can be enabled for PCI devices with the 95.Dq Dv AHC_ALLOW_MEMIO 96configuration option. 97Memory mapped I/O is more efficient than the alternative, programmed I/O. 98Most PCI BIOSes will map devices so that either technique for communicating 99with the card is available. 100In some cases, 101usually when the PCI device is sitting behind a PCI->PCI bridge, 102the BIOS fails to properly initialize the chip for memory mapped I/O. 103The symptom of this problem is usually a system hang if memory mapped I/O 104is attempted. 105Most modern motherboards perform the initialization correctly and work fine 106with this option enabled. 107.Pp 108Per target configuration performed in the 109.Tn SCSI-Select 110menu, accessible at boot 111in 112.No non- Ns Tn EISA 113models, 114or through an 115.Tn EISA 116configuration utility for 117.Tn EISA 118models, 119is honored by this driver with the stipulation that the 120.Tn BIOS 121must be enabled for 122.Tn EISA 123adaptors. This includes synchronous/asynchronous transfers, 124maximum synchronous negotiation rate, 125disconnection, 126the host adapter's SCSI ID, 127and, 128in the case of 129.Tn EISA 130Twin Channel controllers, 131the primary channel selection. 132.Pp 133Note that I/O addresses are determined automatically by the probe routines, 134but care should be taken when using a 284x 135.Pq Tn VESA No local bus controller 136in an 137.Tn EISA 138system. Ensure that the jumpers setting the I/O area for the 284x match the 139.Tn EISA 140slot into which the card is inserted to prevent conflicts with other 141.Tn EISA 142cards. 143.Pp 144Performance and feature sets vary throughout the aic7xxx product line. 145The following table provides a comparison of the different chips supported 146by the 147.Nm 148driver. Note that wide and twin channel features, although always supported 149by a particular chip, may be disabled in a particular motherboard or card 150design. 151.Pp 152.Bd -filled -offset indent 153.Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features 154.Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features" 155aic7770 10 EISA/VL 10MHz 16Bit 4 1 156aic7850 10 PCI/32 10MHz 8Bit 3 157aic7860 10 PCI/32 20MHz 8Bit 3 158aic7870 10 PCI/32 10MHz 16Bit 16 159aic7880 10 PCI/32 20MHz 16Bit 16 160aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 161aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 162aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 163aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 164aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 165.El 166.Pp 167.Bl -enum -compact 168.It 169Multiplexed Twin Channel Device - One controller servicing two busses. 170.It 171Multi-function Twin Channel Device - Two controllers on one chip. 172.It 173Command Channel Secondary DMA Engine - Allows scatter gather list and 174SCB prefetch. 175.It 17664 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA. 177.It 178Block Move Instruction Support - Doubles the speed of certain sequencer 179operations. 180.It 181.Sq Bayonet 182style Scatter Gather Engine - Improves S/G prefetch performance. 183.It 184Queueing Registers - Allows queueing of new transactions without pausing the 185sequencer. 186.El 187.Ed 188.Pp 189 190.Sh SCSI CONTROL BLOCKS (SCBs) 191Every transaction sent to a device on the SCSI bus is assigned a 192.Sq SCSI Control Block 193(SCB). The SCB contains all of the information required by the 194controller to process a transaction. The chip feature table lists 195the number of SCBs that can be stored in on chip memory. All chips 196with model numbers greater than or equal to 7870 allow for the on chip 197SCB space to be augmented with external SRAM up to a maximum of 255 SCBs. 198Very few Adaptec controller have external SRAM. 199 200If external SRAM is not available, SCBs are a limited resource and 201using them in a straight forward manner would only allow us to 202keep as many transactions as there are SCBs outstanding at a time. 203This would not allow enough concurrency to fully utilize the SCSI 204bus and it's devices. The solution to this problem is 205.Em SCB Paging , 206a concept similar to memory paging. SCB paging takes advantage of 207the fact that devices usually disconnect from the SCSI bus for long 208periods of time without talking to the controller. The SCBs 209for disconnected transactions are only of use to the controller 210when the transfer is resumed. When the host queues another transaction 211for the controller to execute, the controller firmware will use a 212free SCB if one is available. Otherwise, the state of the most recently 213disconnected (and therefor most likely to stay disconnected) SCB is 214saved, via dma, to host memory, and the local SCB reused to start 215the new transaction. This allows the controller to queue up to 216255 transactions regardless of the amount of SCB space. Since the 217local SCB space serves as a cache for disconnected transactions, the 218more SCB space available, the less host bus traffic consumed saving 219and restoring SCB data. 220.Sh BUGS 221Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 222.Tn AIC7870 223Rev B in synchronous mode at 10MHz. Controllers with this problem have a 22442 MHz clock crystal on them and run slightly above 10MHz. This confuses 225the drive and hangs the bus. Setting a maximum synchronous negotiation rate 226of 8MHz in the 227.Tn SCSI-Select 228utility 229will allow normal operation. 230.Sh SEE ALSO 231.Xr aha 4 , 232.Xr ahb 4 , 233.Xr cd 4 , 234.Xr scsi 4 , 235.Xr da 4 , 236.Xr sa 4 237.Sh AUTHORS 238The 239.Nm 240driver, the 241.Tn AIC7xxx 242sequencer-code assember, 243and the firmware running on the aic7xxx chips was written by 244.An Justin T. Gibbs . 245.Sh HISTORY 246The 247.Nm 248driver appeared in 249.Fx 2.0 . 250