1.\" Copyright (c) 2010 Konstantin Belousov <kib@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd July 29, 2020 28.Dt AESNI 4 29.Os 30.Sh NAME 31.Nm aesni 32.Nd "driver for the AES and SHA accelerator on x86 CPUs" 33.Sh SYNOPSIS 34To compile this driver into the kernel, 35place the following lines in your 36kernel configuration file: 37.Bd -ragged -offset indent 38.Cd "device crypto" 39.Cd "device cryptodev" 40.Cd "device aesni" 41.Ed 42.Pp 43Alternatively, to load the driver as a 44module at boot time, place the following line in 45.Xr loader.conf 5 : 46.Bd -literal -offset indent 47aesni_load="YES" 48.Ed 49.Sh DESCRIPTION 50Starting with Intel Westmere and AMD Bulldozer, some x86 processors implement a 51new set of instructions called AESNI. 52The set of six instructions accelerates the calculation of the key 53schedule for key lengths of 128, 192, and 256 of the Advanced 54Encryption Standard (AES) symmetric cipher, and provides a hardware 55implementation of the regular and the last encryption and decryption 56rounds. 57.Pp 58The processor capability is reported as AESNI in the Features2 line at boot. 59.Pp 60Starting with the Intel Goldmont and AMD Ryzen microarchitectures, some x86 61processors implement a new set of SHA instructions. 62The set of seven instructions accelerates the calculation of SHA1 and SHA256 63hashes. 64.Pp 65The processor capability is reported as SHA in the Structured Extended Features 66line at boot. 67.Pp 68The 69.Nm 70driver does not attach on systems that lack both CPU capabilities. 71On systems that support only one of AESNI or SHA extensions, the driver will 72attach and support that one function. 73.Pp 74The 75.Nm 76driver registers itself to accelerate AES and SHA operations for 77.Xr crypto 4 . 78Besides speed, the advantage of using the 79.Nm 80driver is that the AESNI operation 81is data-independent, thus eliminating some attack vectors based on 82measuring cache use and timings typically present in table-driven 83implementations. 84.Sh SEE ALSO 85.Xr crypt 3 , 86.Xr crypto 4 , 87.Xr intro 4 , 88.Xr ipsec 4 , 89.Xr padlock 4 , 90.Xr random 4 , 91.Xr crypto 7 , 92.Xr crypto 9 93.Sh HISTORY 94The 95.Nm 96driver first appeared in 97.Fx 9.0 . 98SHA support was added in 99.Fx 12.0 . 100.Sh AUTHORS 101.An -nosplit 102The 103.Nm 104driver was written by 105.An Konstantin Belousov Aq Mt kib@FreeBSD.org 106and 107.An Conrad Meyer Aq Mt cem@FreeBSD.org . 108The key schedule calculation code was adopted from the sample provided 109by Intel and used in the analogous 110.Ox 111driver. 112The hash step intrinsics implementations were supplied by Intel. 113