1.\" Copyright (c) 2010 Konstantin Belousov <kib@FreeBSD.org> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd July 29, 2020 26.Dt AESNI 4 27.Os 28.Sh NAME 29.Nm aesni 30.Nd "driver for the AES and SHA accelerator on x86 CPUs" 31.Sh SYNOPSIS 32To compile this driver into the kernel, 33place the following lines in your 34kernel configuration file: 35.Bd -ragged -offset indent 36.Cd "device crypto" 37.Cd "device cryptodev" 38.Cd "device aesni" 39.Ed 40.Pp 41Alternatively, to load the driver as a 42module at boot time, place the following line in 43.Xr loader.conf 5 : 44.Bd -literal -offset indent 45aesni_load="YES" 46.Ed 47.Sh DESCRIPTION 48Starting with Intel Westmere and AMD Bulldozer, some x86 processors implement a 49new set of instructions called AESNI. 50The set of six instructions accelerates the calculation of the key 51schedule for key lengths of 128, 192, and 256 of the Advanced 52Encryption Standard (AES) symmetric cipher, and provides a hardware 53implementation of the regular and the last encryption and decryption 54rounds. 55.Pp 56The processor capability is reported as AESNI in the Features2 line at boot. 57.Pp 58Starting with the Intel Goldmont and AMD Ryzen microarchitectures, some x86 59processors implement a new set of SHA instructions. 60The set of seven instructions accelerates the calculation of SHA1 and SHA256 61hashes. 62.Pp 63The processor capability is reported as SHA in the Structured Extended Features 64line at boot. 65.Pp 66The 67.Nm 68driver does not attach on systems that lack both CPU capabilities. 69On systems that support only one of AESNI or SHA extensions, the driver will 70attach and support that one function. 71.Pp 72The 73.Nm 74driver registers itself to accelerate AES and SHA operations for 75.Xr crypto 4 . 76Besides speed, the advantage of using the 77.Nm 78driver is that the AESNI operation 79is data-independent, thus eliminating some attack vectors based on 80measuring cache use and timings typically present in table-driven 81implementations. 82.Sh SEE ALSO 83.Xr crypt 3 , 84.Xr crypto 4 , 85.Xr intro 4 , 86.Xr ipsec 4 , 87.Xr padlock 4 , 88.Xr random 4 , 89.Xr crypto 7 , 90.Xr crypto 9 91.Sh HISTORY 92The 93.Nm 94driver first appeared in 95.Fx 9.0 . 96SHA support was added in 97.Fx 12.0 . 98.Sh AUTHORS 99.An -nosplit 100The 101.Nm 102driver was written by 103.An Konstantin Belousov Aq Mt kib@FreeBSD.org 104and 105.An Conrad Meyer Aq Mt cem@FreeBSD.org . 106The key schedule calculation code was adopted from the sample provided 107by Intel and used in the analogous 108.Ox 109driver. 110The hash step intrinsics implementations were supplied by Intel. 111