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Title "OPENSSL_ARMCAP 3ossl" For nroff, turn off justification. Always turn off hyphenation; it makes
way too many mistakes in technical documents.
OPENSSL_armcap - the Arm processor capabilities vector Header "SYNOPSIS" .Vb 1 env OPENSSL_armcap=... <application> .Ve Header "DESCRIPTION" libcrypto supports a range of Arm instruction set extensions. These extensions are represented by bits in the Arm processor capabilities vector. When libcrypto initializes, it stores the results returned by Arm CPU capabilities detection logic in the Arm processor capabilities vector. The CPU capabilities detection methods are OS-dependent, using a combination of information gathered by the kernel during boot, and probe functions that attempt to execute instructions and trap illegal instruction signals with a signal handler.

To override the set of extensions available to an application, set the \fBOPENSSL_armcap environment variable before starting the application. The environment variable is assigned a numerical value that denotes the bits in the Arm processor capabilities vector. The arm_arch.h header file defines the possible values, which are explained in detail below.

Multiple extensions are enabled by logically OR-ing the values that represent the desired extensions.

\fBNotes: Attempting to executing an instruction from an extension that the target CPU does not support will result in an illegal instruction exception (SIGILL).

Please note that not all possible values in the Arm processor capabilities vector are actual processor capabilities. Some values represent OpenSSL performance preferences for some implementations which only make sense on specific CPUs.

The following extensions are defined:

Item "0x0001" Name: ARMV7_NEON .Sp Meaning: Indicates support for the Armv7 Neon SIMD extensions on the processor. .Sp Effect: Enables various Armv7 Neon SIMD implementations. Item "0x00002" Name: ARMV7_TICK .Sp Meaning: Indicates support for the Armv7 system timer on the processor. .Sp Effect: This is used as a seed for some random number generators. Item "0x00004" Name: ARMV8_AES .Sp Meaning: Indicates support for the Armv8.0 AES hardware-acceleration extensions on the processor. .Sp Effect: Enables various Armv8.0 AES hardware-accelerated implementations. Item "0x00008" Name: ARMV8_SHA1 .Sp Meaning: Indicates support for the Armv8.0 SHA1 hardware-acceleration extensions on the processor. .Sp Effect: Enables various Armv8.0 SHA1 hardware-accelerated implementations. Item "0x00010" Name: ARMV8_SHA256 .Sp Meaning: Indicates support for the Armv8.0 SHA256 hardware-acceleration extensions on the processor. .Sp Effect: Enables various Armv8.0 SHA256 hardware-accelerated implementations. Item "0x00020" Name: ARMV8_PMULL .Sp Meaning: Indicates support for the Armv8.0 polynomial multiplication hardware-acceleration extensions on the processor. .Sp Effect: Used to hardware-accelerate polynomial multiplication, for example in AES-GCM. Item "0x00040" Name: ARMV8_SHA512 .Sp Meaning: Indicates support for the Armv8.2 SHA512 hardware-acceleration extensions on the processor. .Sp Effect: Enables Armv8.2 SHA512 hardware-accelerated implementations. Item "0x00080" Name: ARMV8_CPUID .Sp Meaning: Indicates support for the Armv8.0 hardware identification extensions on the processor. .Sp Effect: Allows implementations to change their behaviour, dependant on the processor platform in order to achieve better performance. Item "0x00100" Name: ARMV8_RNG .Sp Meaning: Indicates support for the Armv8.5 hardware random number generation extensions on the processor. .Sp Effect: Enables hardware random number generation on supported AArch64 processors. Item "0x00200" Name: ARMV8_SM3 .Sp Meaning: Indicates support for the Armv8.2 SM3 hardware-acceleration extensions on the processor. .Sp Effect: Enables Armv8.2 SM3 hardware-accelerated implementations. Item "0x00400" Name: ARMV8_SM4 .Sp Meaning: Indicates support for the Armv8.2 SM4 hardware-acceleration extensions on the processor. .Sp Effect: Enables Armv8.2 SM4 hardware-accelerated implementations. Item "0x00800" Name: ARMV8_SHA3 .Sp Meaning: Indicates support for the Armv8.2 SHA3 hardware-acceleration extensions on the processor. .Sp Effect: Enables SHA3 hardware-accelerated implementations (see also ARMV8_HAVE_SHA3_AND_WORTH_USING). Item "0x01000" Name: ARMV8_UNROLL8_EOR3 .Sp Meaning: Indicates support for the Arm EOR3 instruction, which is a part of the Armv8.2 SHA3 extensions, and enables 8x Loop unrolling in the AES-CTR implementation. .Sp Effect: Enables the 8x loop unrolling utilising EOR3 implementation of AES-CTR on platforms that support the SHA3 extension and have enough vector bandwidth. Item "0x02000" Name: ARMV8_SVE .Sp Meaning: Indicates support for the Armv8.2 SVE hardware extension on the processor. .Sp Effect: Enables various Armv8.2 SVE implementations. Item "0x04000" Name: ARMV9_SVE2 .Sp Meaning: Indicates support for the Armv9.0 SVE2 hardware extension on the processor. .Sp Effect: Enables various Armv9.0 SVE2 implementations. Item "0x08000" Name: ARMV8_HAVE_SHA3_AND_WORTH_USING .Sp Meaning: Indicates support for the Armv8.2 SHA3 hardware-acceleration extensions on the processor, and that the hardware bandwidth is sufficient for it to be worth using. .Sp Effect: On certain Apple platforms, although the SHA3 extension is supported, it is actually slower than other implementations. This flag disables the hardware-accelerated SHA3 implementations on these platforms. Item "0x10000" Name: ARMV8_UNROLL12_EOR3 .Sp Meaning: Indicates support for the Arm EOR3 instruction, which is a part of the Armv8.2 SHA3 extensions, and enables 12x loop unrolling in the AES-CTR implementation. .Sp Effect: Enables the 12x loop unrolling utilising EOR3 implementation of AES-CTR on platforms that support the extension and have enough vector bandwidth. Item "0x20000" Name: ARMV9_SVE2_POLY1305 .Sp Meaning: Indicates support for the Armv9.0 SVE2 hardware extension, and enables its use in the Poly1305 implementation. .Sp Effect: Enables the Armv9.0 SVE2 Poly1305 implementation if SVE2 is enabled, the vector length is greater than 128 bits, and the vector length is a power of 2. Header "RETURN VALUES" Not available. Header "EXAMPLES" Check currently detected capabilities:

.Vb 2 $ openssl info -cpusettings OPENSSL_armcap=0x987d .Ve

The detected capabilities in the above example indicate that ARMV7_NEON, ARMV8_AES, ARMV8_SHA1, ARMV8_SHA256, ARMV8_PMULL, ARMV8_SHA512, ARMV8_SHA3, ARMV8_UNROLL8_EOR3, and ARMV8_HAVE_SHA3_AND_WORTH_USING are enabled.

Disable all instruction set extensions:

.Vb 1 export OPENSSL_armcap=0x00 .Ve

Header "COPYRIGHT" Copyright 2026 The OpenSSL Project Authors. All Rights Reserved.

Licensed under the Apache License 2.0 (the "License"). You may not use this file except in compliance with the License. You can obtain a copy in the file LICENSE in the source distribution or at <https://www.openssl.org/source/license.html>.