1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * Copyright (C) 2018-2019 Alexander Motin <mav@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 32 #include <ctype.h> 33 #include <err.h> 34 #include <fcntl.h> 35 #include <stddef.h> 36 #include <stdio.h> 37 #include <stdlib.h> 38 #include <string.h> 39 #include <unistd.h> 40 41 #include "nvmecontrol.h" 42 #include "nvmecontrol_ext.h" 43 44 void 45 nvme_print_controller(struct nvme_controller_data *cdata) 46 { 47 uint8_t str[128]; 48 char cbuf[UINT128_DIG + 1]; 49 uint16_t oncs, oacs; 50 uint8_t compare, write_unc, dsm, t; 51 uint8_t security, fmt, fw, nsmgmt; 52 uint8_t fw_slot1_ro, fw_num_slots; 53 uint8_t ns_smart; 54 uint8_t sqes_max, sqes_min; 55 uint8_t cqes_max, cqes_min; 56 uint8_t fwug; 57 58 oncs = cdata->oncs; 59 compare = (oncs >> NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT) & 60 NVME_CTRLR_DATA_ONCS_COMPARE_MASK; 61 write_unc = (oncs >> NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT) & 62 NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK; 63 dsm = (oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & 64 NVME_CTRLR_DATA_ONCS_DSM_MASK; 65 66 oacs = cdata->oacs; 67 security = (oacs >> NVME_CTRLR_DATA_OACS_SECURITY_SHIFT) & 68 NVME_CTRLR_DATA_OACS_SECURITY_MASK; 69 fmt = (oacs >> NVME_CTRLR_DATA_OACS_FORMAT_SHIFT) & 70 NVME_CTRLR_DATA_OACS_FORMAT_MASK; 71 fw = (oacs >> NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT) & 72 NVME_CTRLR_DATA_OACS_FIRMWARE_MASK; 73 nsmgmt = (oacs >> NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT) & 74 NVME_CTRLR_DATA_OACS_NSMGMT_MASK; 75 76 fw_num_slots = (cdata->frmw >> NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT) & 77 NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK; 78 fw_slot1_ro = (cdata->frmw >> NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT) & 79 NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK; 80 fwug = cdata->fwug; 81 82 ns_smart = (cdata->lpa >> NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT) & 83 NVME_CTRLR_DATA_LPA_NS_SMART_MASK; 84 85 sqes_min = (cdata->sqes >> NVME_CTRLR_DATA_SQES_MIN_SHIFT) & 86 NVME_CTRLR_DATA_SQES_MIN_MASK; 87 sqes_max = (cdata->sqes >> NVME_CTRLR_DATA_SQES_MAX_SHIFT) & 88 NVME_CTRLR_DATA_SQES_MAX_MASK; 89 90 cqes_min = (cdata->cqes >> NVME_CTRLR_DATA_CQES_MIN_SHIFT) & 91 NVME_CTRLR_DATA_CQES_MIN_MASK; 92 cqes_max = (cdata->cqes >> NVME_CTRLR_DATA_CQES_MAX_SHIFT) & 93 NVME_CTRLR_DATA_CQES_MAX_MASK; 94 95 printf("Controller Capabilities/Features\n"); 96 printf("================================\n"); 97 printf("Vendor ID: %04x\n", cdata->vid); 98 printf("Subsystem Vendor ID: %04x\n", cdata->ssvid); 99 nvme_strvis(str, cdata->sn, sizeof(str), NVME_SERIAL_NUMBER_LENGTH); 100 printf("Serial Number: %s\n", str); 101 nvme_strvis(str, cdata->mn, sizeof(str), NVME_MODEL_NUMBER_LENGTH); 102 printf("Model Number: %s\n", str); 103 nvme_strvis(str, cdata->fr, sizeof(str), NVME_FIRMWARE_REVISION_LENGTH); 104 printf("Firmware Version: %s\n", str); 105 printf("Recommended Arb Burst: %d\n", cdata->rab); 106 printf("IEEE OUI Identifier: %02x %02x %02x\n", 107 cdata->ieee[2], cdata->ieee[1], cdata->ieee[0]); 108 printf("Multi-Path I/O Capabilities: %s%s%s%s%s\n", 109 (cdata->mic == 0) ? "Not Supported" : "", 110 ((cdata->mic >> NVME_CTRLR_DATA_MIC_ANAR_SHIFT) & 111 NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "Asymmetric, " : "", 112 ((cdata->mic >> NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT) & 113 NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "SR-IOV VF, " : "", 114 ((cdata->mic >> NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT) & 115 NVME_CTRLR_DATA_MIC_MCTRLRS_MASK) ? "Multiple controllers, " : "", 116 ((cdata->mic >> NVME_CTRLR_DATA_MIC_MPORTS_SHIFT) & 117 NVME_CTRLR_DATA_MIC_MPORTS_MASK) ? "Multiple ports" : ""); 118 /* TODO: Use CAP.MPSMIN to determine true memory page size. */ 119 printf("Max Data Transfer Size: "); 120 if (cdata->mdts == 0) 121 printf("Unlimited\n"); 122 else 123 printf("%ld bytes\n", PAGE_SIZE * (1L << cdata->mdts)); 124 printf("Sanitize Crypto Erase: %s\n", 125 ((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_CES_SHIFT) & 126 NVME_CTRLR_DATA_SANICAP_CES_MASK) ? 127 "Supported" : "Not Supported"); 128 printf("Sanitize Block Erase: %s\n", 129 ((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_BES_SHIFT) & 130 NVME_CTRLR_DATA_SANICAP_BES_MASK) ? 131 "Supported" : "Not Supported"); 132 printf("Sanitize Overwrite: %s\n", 133 ((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_OWS_SHIFT) & 134 NVME_CTRLR_DATA_SANICAP_OWS_MASK) ? 135 "Supported" : "Not Supported"); 136 printf("Sanitize NDI: %s\n", 137 ((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_NDI_SHIFT) & 138 NVME_CTRLR_DATA_SANICAP_NDI_MASK) ? 139 "Supported" : "Not Supported"); 140 printf("Sanitize NODMMAS: "); 141 switch (((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT) & 142 NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK)) { 143 case NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF: 144 printf("Undefined\n"); 145 break; 146 case NVME_CTRLR_DATA_SANICAP_NODMMAS_NO: 147 printf("No\n"); 148 break; 149 case NVME_CTRLR_DATA_SANICAP_NODMMAS_YES: 150 printf("Yes\n"); 151 break; 152 default: 153 printf("Unknown\n"); 154 break; 155 } 156 printf("Controller ID: 0x%04x\n", cdata->ctrlr_id); 157 printf("Version: %d.%d.%d\n", 158 (cdata->ver >> 16) & 0xffff, (cdata->ver >> 8) & 0xff, 159 cdata->ver & 0xff); 160 printf("\n"); 161 162 printf("Admin Command Set Attributes\n"); 163 printf("============================\n"); 164 printf("Security Send/Receive: %s\n", 165 security ? "Supported" : "Not Supported"); 166 printf("Format NVM: %s\n", 167 fmt ? "Supported" : "Not Supported"); 168 printf("Firmware Activate/Download: %s\n", 169 fw ? "Supported" : "Not Supported"); 170 printf("Namespace Management: %s\n", 171 nsmgmt ? "Supported" : "Not Supported"); 172 printf("Device Self-test: %sSupported\n", 173 ((oacs >> NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT) & 174 NVME_CTRLR_DATA_OACS_SELFTEST_MASK) ? "" : "Not "); 175 printf("Directives: %sSupported\n", 176 ((oacs >> NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT) & 177 NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK) ? "" : "Not "); 178 printf("NVMe-MI Send/Receive: %sSupported\n", 179 ((oacs >> NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT) & 180 NVME_CTRLR_DATA_OACS_NVMEMI_MASK) ? "" : "Not "); 181 printf("Virtualization Management: %sSupported\n", 182 ((oacs >> NVME_CTRLR_DATA_OACS_VM_SHIFT) & 183 NVME_CTRLR_DATA_OACS_VM_MASK) ? "" : "Not "); 184 printf("Doorbell Buffer Config: %sSupported\n", 185 ((oacs >> NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT) & 186 NVME_CTRLR_DATA_OACS_DBBUFFER_MASK) ? "" : "Not "); 187 printf("Get LBA Status: %sSupported\n", 188 ((oacs >> NVME_CTRLR_DATA_OACS_GETLBA_SHIFT) & 189 NVME_CTRLR_DATA_OACS_GETLBA_MASK) ? "" : "Not "); 190 printf("Sanitize: "); 191 if (cdata->sanicap != 0) { 192 printf("%s%s%s\n", 193 ((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_CES_SHIFT) & 194 NVME_CTRLR_DATA_SANICAP_CES_MASK) ? "crypto, " : "", 195 ((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_BES_SHIFT) & 196 NVME_CTRLR_DATA_SANICAP_BES_MASK) ? "block, " : "", 197 ((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_OWS_SHIFT) & 198 NVME_CTRLR_DATA_SANICAP_OWS_MASK) ? "overwrite" : ""); 199 } else { 200 printf("Not Supported\n"); 201 } 202 printf("Abort Command Limit: %d\n", cdata->acl+1); 203 printf("Async Event Request Limit: %d\n", cdata->aerl+1); 204 printf("Number of Firmware Slots: %d\n", fw_num_slots); 205 printf("Firmware Slot 1 Read-Only: %s\n", fw_slot1_ro ? "Yes" : "No"); 206 printf("Per-Namespace SMART Log: %s\n", 207 ns_smart ? "Yes" : "No"); 208 printf("Error Log Page Entries: %d\n", cdata->elpe+1); 209 printf("Number of Power States: %d\n", cdata->npss+1); 210 if (cdata->ver >= 0x010200) { 211 printf("Total NVM Capacity: %s bytes\n", 212 uint128_to_str(to128(cdata->untncap.tnvmcap), 213 cbuf, sizeof(cbuf))); 214 printf("Unallocated NVM Capacity: %s bytes\n", 215 uint128_to_str(to128(cdata->untncap.unvmcap), 216 cbuf, sizeof(cbuf))); 217 } 218 printf("Firmware Update Granularity: %02x ", fwug); 219 if (fwug == 0) 220 printf("(Not Reported)\n"); 221 else if (fwug == 0xFF) 222 printf("(No Granularity)\n"); 223 else 224 printf("(%d bytes)\n", ((uint32_t)fwug << 12)); 225 printf("Host Buffer Preferred Size: %llu bytes\n", 226 (long long unsigned)cdata->hmpre * 4096); 227 printf("Host Buffer Minimum Size: %llu bytes\n", 228 (long long unsigned)cdata->hmmin * 4096); 229 230 printf("\n"); 231 printf("NVM Command Set Attributes\n"); 232 printf("==========================\n"); 233 printf("Submission Queue Entry Size\n"); 234 printf(" Max: %d\n", 1 << sqes_max); 235 printf(" Min: %d\n", 1 << sqes_min); 236 printf("Completion Queue Entry Size\n"); 237 printf(" Max: %d\n", 1 << cqes_max); 238 printf(" Min: %d\n", 1 << cqes_min); 239 printf("Number of Namespaces: %d\n", cdata->nn); 240 printf("Compare Command: %s\n", 241 compare ? "Supported" : "Not Supported"); 242 printf("Write Uncorrectable Command: %s\n", 243 write_unc ? "Supported" : "Not Supported"); 244 printf("Dataset Management Command: %s\n", 245 dsm ? "Supported" : "Not Supported"); 246 printf("Write Zeroes Command: %sSupported\n", 247 ((oncs >> NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT) & 248 NVME_CTRLR_DATA_ONCS_WRZERO_MASK) ? "" : "Not "); 249 printf("Save Features: %sSupported\n", 250 ((oncs >> NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT) & 251 NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK) ? "" : "Not "); 252 printf("Reservations: %sSupported\n", 253 ((oncs >> NVME_CTRLR_DATA_ONCS_RESERV_SHIFT) & 254 NVME_CTRLR_DATA_ONCS_RESERV_MASK) ? "" : "Not "); 255 printf("Timestamp feature: %sSupported\n", 256 ((oncs >> NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT) & 257 NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK) ? "" : "Not "); 258 printf("Verify feature: %sSupported\n", 259 ((oncs >> NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT) & 260 NVME_CTRLR_DATA_ONCS_VERIFY_MASK) ? "" : "Not "); 261 printf("Fused Operation Support: %s%s\n", 262 (cdata->fuses == 0) ? "Not Supported" : "", 263 ((cdata->fuses >> NVME_CTRLR_DATA_FUSES_CNW_SHIFT) & 264 NVME_CTRLR_DATA_FUSES_CNW_MASK) ? "Compare and Write" : ""); 265 printf("Format NVM Attributes: %s%s Erase, %s Format\n", 266 ((cdata->fna >> NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT) & 267 NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK) ? "Crypto Erase, " : "", 268 ((cdata->fna >> NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT) & 269 NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK) ? "All-NVM" : "Per-NS", 270 ((cdata->fna >> NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT) & 271 NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK) ? "All-NVM" : "Per-NS"); 272 t = (cdata->vwc >> NVME_CTRLR_DATA_VWC_ALL_SHIFT) & 273 NVME_CTRLR_DATA_VWC_ALL_MASK; 274 printf("Volatile Write Cache: %s%s\n", 275 ((cdata->vwc >> NVME_CTRLR_DATA_VWC_PRESENT_SHIFT) & 276 NVME_CTRLR_DATA_VWC_PRESENT_MASK) ? "Present" : "Not Present", 277 (t == NVME_CTRLR_DATA_VWC_ALL_NO) ? ", no flush all" : 278 (t == NVME_CTRLR_DATA_VWC_ALL_YES) ? ", flush all" : ""); 279 280 if (cdata->ver >= 0x010201) 281 printf("\nNVM Subsystem Name: %.256s\n", cdata->subnqn); 282 } 283