1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifdef __arm__ 30 #include <arm/fenv.h> 31 #else /* __arm__ */ 32 33 #ifndef _FENV_H_ 34 #define _FENV_H_ 35 36 #include <sys/_types.h> 37 38 #ifndef __fenv_static 39 #define __fenv_static static 40 #endif 41 42 /* The high 32 bits contain fpcr, low 32 contain fpsr. */ 43 typedef __uint64_t fenv_t; 44 typedef __uint64_t fexcept_t; 45 46 /* Exception flags */ 47 #define FE_INVALID 0x00000001 48 #define FE_DIVBYZERO 0x00000002 49 #define FE_OVERFLOW 0x00000004 50 #define FE_UNDERFLOW 0x00000008 51 #define FE_INEXACT 0x00000010 52 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 53 FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 54 55 /* 56 * Rounding modes 57 * 58 * We can't just use the hardware bit values here, because that would 59 * make FE_UPWARD and FE_DOWNWARD negative, which is not allowed. 60 */ 61 #define FE_TONEAREST 0x0 62 #define FE_UPWARD 0x1 63 #define FE_DOWNWARD 0x2 64 #define FE_TOWARDZERO 0x3 65 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 66 FE_UPWARD | FE_TOWARDZERO) 67 #define _ROUND_SHIFT 22 68 69 __BEGIN_DECLS 70 71 /* Default floating-point environment */ 72 extern const fenv_t __fe_dfl_env; 73 #define FE_DFL_ENV (&__fe_dfl_env) 74 75 /* We need to be able to map status flag positions to mask flag positions */ 76 #define _FPUSW_SHIFT 8 77 #define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) 78 79 #define __mrs_fpcr(__r) __asm __volatile("mrs %0, fpcr" : "=r" (__r)) 80 #define __msr_fpcr(__r) __asm __volatile("msr fpcr, %0" : : "r" (__r)) 81 82 #define __mrs_fpsr(__r) __asm __volatile("mrs %0, fpsr" : "=r" (__r)) 83 #define __msr_fpsr(__r) __asm __volatile("msr fpsr, %0" : : "r" (__r)) 84 85 __fenv_static __inline int 86 feclearexcept(int __excepts) 87 { 88 fexcept_t __r; 89 90 __mrs_fpsr(__r); 91 __r &= ~__excepts; 92 __msr_fpsr(__r); 93 return (0); 94 } 95 96 __fenv_static inline int 97 fegetexceptflag(fexcept_t *__flagp, int __excepts) 98 { 99 fexcept_t __r; 100 101 __mrs_fpsr(__r); 102 *__flagp = __r & __excepts; 103 return (0); 104 } 105 106 __fenv_static inline int 107 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 108 { 109 fexcept_t __r; 110 111 __mrs_fpsr(__r); 112 __r &= ~__excepts; 113 __r |= *__flagp & __excepts; 114 __msr_fpsr(__r); 115 return (0); 116 } 117 118 __fenv_static inline int 119 feraiseexcept(int __excepts) 120 { 121 fexcept_t __r; 122 123 __mrs_fpsr(__r); 124 __r |= __excepts; 125 __msr_fpsr(__r); 126 return (0); 127 } 128 129 __fenv_static inline int 130 fetestexcept(int __excepts) 131 { 132 fexcept_t __r; 133 134 __mrs_fpsr(__r); 135 return (__r & __excepts); 136 } 137 138 __fenv_static inline int 139 fegetround(void) 140 { 141 fenv_t __r; 142 143 __mrs_fpcr(__r); 144 return ((__r >> _ROUND_SHIFT) & _ROUND_MASK); 145 } 146 147 __fenv_static inline int 148 fesetround(int __round) 149 { 150 fenv_t __r; 151 152 if (__round & ~_ROUND_MASK) 153 return (-1); 154 __mrs_fpcr(__r); 155 __r &= ~(_ROUND_MASK << _ROUND_SHIFT); 156 __r |= __round << _ROUND_SHIFT; 157 __msr_fpcr(__r); 158 return (0); 159 } 160 161 __fenv_static inline int 162 fegetenv(fenv_t *__envp) 163 { 164 __uint64_t fpcr; 165 __uint64_t fpsr; 166 167 __mrs_fpcr(fpcr); 168 __mrs_fpsr(fpsr); 169 *__envp = fpsr | (fpcr << 32); 170 171 return (0); 172 } 173 174 __fenv_static inline int 175 feholdexcept(fenv_t *__envp) 176 { 177 fenv_t __r; 178 179 __mrs_fpcr(__r); 180 *__envp = __r << 32; 181 __r &= ~(_ENABLE_MASK); 182 __msr_fpcr(__r); 183 184 __mrs_fpsr(__r); 185 *__envp |= (__uint32_t)__r; 186 __r &= ~(_ENABLE_MASK); 187 __msr_fpsr(__r); 188 return (0); 189 } 190 191 __fenv_static inline int 192 fesetenv(const fenv_t *__envp) 193 { 194 195 __msr_fpcr((*__envp) >> 32); 196 __msr_fpsr((fenv_t)(__uint32_t)*__envp); 197 return (0); 198 } 199 200 __fenv_static inline int 201 feupdateenv(const fenv_t *__envp) 202 { 203 fexcept_t __r; 204 205 __mrs_fpsr(__r); 206 fesetenv(__envp); 207 feraiseexcept(__r & FE_ALL_EXCEPT); 208 return (0); 209 } 210 211 #if __BSD_VISIBLE 212 213 /* We currently provide no external definitions of the functions below. */ 214 215 static inline int 216 feenableexcept(int __mask) 217 { 218 fenv_t __old_r, __new_r; 219 220 __mrs_fpcr(__old_r); 221 __new_r = __old_r | ((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); 222 __msr_fpcr(__new_r); 223 return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); 224 } 225 226 static inline int 227 fedisableexcept(int __mask) 228 { 229 fenv_t __old_r, __new_r; 230 231 __mrs_fpcr(__old_r); 232 __new_r = __old_r & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); 233 __msr_fpcr(__new_r); 234 return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); 235 } 236 237 static inline int 238 fegetexcept(void) 239 { 240 fenv_t __r; 241 242 __mrs_fpcr(__r); 243 return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT); 244 } 245 246 #endif /* __BSD_VISIBLE */ 247 248 __END_DECLS 249 250 #endif /* !_FENV_H_ */ 251 252 #endif /* __arm__ */ 253