1[ 2 { 3 "EventCode": "0x14", 4 "Counter": "0,1,2,3", 5 "UMask": "0x1", 6 "EventName": "ARITH.CYCLES_DIV_BUSY", 7 "SampleAfterValue": "2000000", 8 "BriefDescription": "Cycles the divider is busy" 9 }, 10 { 11 "EventCode": "0x14", 12 "Invert": "1", 13 "Counter": "0,1,2,3", 14 "UMask": "0x1", 15 "EventName": "ARITH.DIV", 16 "SampleAfterValue": "2000000", 17 "BriefDescription": "Divide Operations executed", 18 "CounterMask": "1", 19 "EdgeDetect": "1" 20 }, 21 { 22 "EventCode": "0x14", 23 "Counter": "0,1,2,3", 24 "UMask": "0x2", 25 "EventName": "ARITH.MUL", 26 "SampleAfterValue": "2000000", 27 "BriefDescription": "Multiply operations executed" 28 }, 29 { 30 "EventCode": "0xE6", 31 "Counter": "0,1,2,3", 32 "UMask": "0x2", 33 "EventName": "BACLEAR.BAD_TARGET", 34 "SampleAfterValue": "2000000", 35 "BriefDescription": "BACLEAR asserted with bad target address" 36 }, 37 { 38 "EventCode": "0xE6", 39 "Counter": "0,1,2,3", 40 "UMask": "0x1", 41 "EventName": "BACLEAR.CLEAR", 42 "SampleAfterValue": "2000000", 43 "BriefDescription": "BACLEAR asserted, regardless of cause " 44 }, 45 { 46 "EventCode": "0xA7", 47 "Counter": "0,1,2,3", 48 "UMask": "0x1", 49 "EventName": "BACLEAR_FORCE_IQ", 50 "SampleAfterValue": "2000000", 51 "BriefDescription": "Instruction queue forced BACLEAR" 52 }, 53 { 54 "EventCode": "0xE0", 55 "Counter": "0,1,2,3", 56 "UMask": "0x1", 57 "EventName": "BR_INST_DECODED", 58 "SampleAfterValue": "2000000", 59 "BriefDescription": "Branch instructions decoded" 60 }, 61 { 62 "EventCode": "0x88", 63 "Counter": "0,1,2,3", 64 "UMask": "0x7f", 65 "EventName": "BR_INST_EXEC.ANY", 66 "SampleAfterValue": "200000", 67 "BriefDescription": "Branch instructions executed" 68 }, 69 { 70 "EventCode": "0x88", 71 "Counter": "0,1,2,3", 72 "UMask": "0x1", 73 "EventName": "BR_INST_EXEC.COND", 74 "SampleAfterValue": "200000", 75 "BriefDescription": "Conditional branch instructions executed" 76 }, 77 { 78 "EventCode": "0x88", 79 "Counter": "0,1,2,3", 80 "UMask": "0x2", 81 "EventName": "BR_INST_EXEC.DIRECT", 82 "SampleAfterValue": "200000", 83 "BriefDescription": "Unconditional branches executed" 84 }, 85 { 86 "EventCode": "0x88", 87 "Counter": "0,1,2,3", 88 "UMask": "0x10", 89 "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", 90 "SampleAfterValue": "20000", 91 "BriefDescription": "Unconditional call branches executed" 92 }, 93 { 94 "EventCode": "0x88", 95 "Counter": "0,1,2,3", 96 "UMask": "0x20", 97 "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", 98 "SampleAfterValue": "20000", 99 "BriefDescription": "Indirect call branches executed" 100 }, 101 { 102 "EventCode": "0x88", 103 "Counter": "0,1,2,3", 104 "UMask": "0x4", 105 "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", 106 "SampleAfterValue": "20000", 107 "BriefDescription": "Indirect non call branches executed" 108 }, 109 { 110 "EventCode": "0x88", 111 "Counter": "0,1,2,3", 112 "UMask": "0x30", 113 "EventName": "BR_INST_EXEC.NEAR_CALLS", 114 "SampleAfterValue": "20000", 115 "BriefDescription": "Call branches executed" 116 }, 117 { 118 "EventCode": "0x88", 119 "Counter": "0,1,2,3", 120 "UMask": "0x7", 121 "EventName": "BR_INST_EXEC.NON_CALLS", 122 "SampleAfterValue": "200000", 123 "BriefDescription": "All non call branches executed" 124 }, 125 { 126 "EventCode": "0x88", 127 "Counter": "0,1,2,3", 128 "UMask": "0x8", 129 "EventName": "BR_INST_EXEC.RETURN_NEAR", 130 "SampleAfterValue": "20000", 131 "BriefDescription": "Indirect return branches executed" 132 }, 133 { 134 "EventCode": "0x88", 135 "Counter": "0,1,2,3", 136 "UMask": "0x40", 137 "EventName": "BR_INST_EXEC.TAKEN", 138 "SampleAfterValue": "200000", 139 "BriefDescription": "Taken branches executed" 140 }, 141 { 142 "PEBS": "1", 143 "EventCode": "0xC4", 144 "Counter": "0,1,2,3", 145 "UMask": "0x4", 146 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 147 "SampleAfterValue": "200000", 148 "BriefDescription": "Retired branch instructions (Precise Event)" 149 }, 150 { 151 "PEBS": "1", 152 "EventCode": "0xC4", 153 "Counter": "0,1,2,3", 154 "UMask": "0x1", 155 "EventName": "BR_INST_RETIRED.CONDITIONAL", 156 "SampleAfterValue": "200000", 157 "BriefDescription": "Retired conditional branch instructions (Precise Event)" 158 }, 159 { 160 "PEBS": "1", 161 "EventCode": "0xC4", 162 "Counter": "0,1,2,3", 163 "UMask": "0x2", 164 "EventName": "BR_INST_RETIRED.NEAR_CALL", 165 "SampleAfterValue": "20000", 166 "BriefDescription": "Retired near call instructions (Precise Event)" 167 }, 168 { 169 "EventCode": "0x89", 170 "Counter": "0,1,2,3", 171 "UMask": "0x7f", 172 "EventName": "BR_MISP_EXEC.ANY", 173 "SampleAfterValue": "20000", 174 "BriefDescription": "Mispredicted branches executed" 175 }, 176 { 177 "EventCode": "0x89", 178 "Counter": "0,1,2,3", 179 "UMask": "0x1", 180 "EventName": "BR_MISP_EXEC.COND", 181 "SampleAfterValue": "20000", 182 "BriefDescription": "Mispredicted conditional branches executed" 183 }, 184 { 185 "EventCode": "0x89", 186 "Counter": "0,1,2,3", 187 "UMask": "0x2", 188 "EventName": "BR_MISP_EXEC.DIRECT", 189 "SampleAfterValue": "20000", 190 "BriefDescription": "Mispredicted unconditional branches executed" 191 }, 192 { 193 "EventCode": "0x89", 194 "Counter": "0,1,2,3", 195 "UMask": "0x10", 196 "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", 197 "SampleAfterValue": "2000", 198 "BriefDescription": "Mispredicted non call branches executed" 199 }, 200 { 201 "EventCode": "0x89", 202 "Counter": "0,1,2,3", 203 "UMask": "0x20", 204 "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", 205 "SampleAfterValue": "2000", 206 "BriefDescription": "Mispredicted indirect call branches executed" 207 }, 208 { 209 "EventCode": "0x89", 210 "Counter": "0,1,2,3", 211 "UMask": "0x4", 212 "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", 213 "SampleAfterValue": "2000", 214 "BriefDescription": "Mispredicted indirect non call branches executed" 215 }, 216 { 217 "EventCode": "0x89", 218 "Counter": "0,1,2,3", 219 "UMask": "0x30", 220 "EventName": "BR_MISP_EXEC.NEAR_CALLS", 221 "SampleAfterValue": "2000", 222 "BriefDescription": "Mispredicted call branches executed" 223 }, 224 { 225 "EventCode": "0x89", 226 "Counter": "0,1,2,3", 227 "UMask": "0x7", 228 "EventName": "BR_MISP_EXEC.NON_CALLS", 229 "SampleAfterValue": "20000", 230 "BriefDescription": "Mispredicted non call branches executed" 231 }, 232 { 233 "EventCode": "0x89", 234 "Counter": "0,1,2,3", 235 "UMask": "0x8", 236 "EventName": "BR_MISP_EXEC.RETURN_NEAR", 237 "SampleAfterValue": "2000", 238 "BriefDescription": "Mispredicted return branches executed" 239 }, 240 { 241 "EventCode": "0x89", 242 "Counter": "0,1,2,3", 243 "UMask": "0x40", 244 "EventName": "BR_MISP_EXEC.TAKEN", 245 "SampleAfterValue": "20000", 246 "BriefDescription": "Mispredicted taken branches executed" 247 }, 248 { 249 "PEBS": "1", 250 "EventCode": "0xC5", 251 "Counter": "0,1,2,3", 252 "UMask": "0x4", 253 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 254 "SampleAfterValue": "20000", 255 "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" 256 }, 257 { 258 "PEBS": "1", 259 "EventCode": "0xC5", 260 "Counter": "0,1,2,3", 261 "UMask": "0x1", 262 "EventName": "BR_MISP_RETIRED.CONDITIONAL", 263 "SampleAfterValue": "20000", 264 "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" 265 }, 266 { 267 "PEBS": "1", 268 "EventCode": "0xC5", 269 "Counter": "0,1,2,3", 270 "UMask": "0x2", 271 "EventName": "BR_MISP_RETIRED.NEAR_CALL", 272 "SampleAfterValue": "2000", 273 "BriefDescription": "Mispredicted near retired calls (Precise Event)" 274 }, 275 { 276 "EventCode": "0x0", 277 "Counter": "Fixed counter 3", 278 "UMask": "0x0", 279 "EventName": "CPU_CLK_UNHALTED.REF", 280 "SampleAfterValue": "2000000", 281 "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" 282 }, 283 { 284 "EventCode": "0x3C", 285 "Counter": "0,1,2,3", 286 "UMask": "0x1", 287 "EventName": "CPU_CLK_UNHALTED.REF_P", 288 "SampleAfterValue": "100000", 289 "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" 290 }, 291 { 292 "EventCode": "0x0", 293 "Counter": "Fixed counter 2", 294 "UMask": "0x0", 295 "EventName": "CPU_CLK_UNHALTED.THREAD", 296 "SampleAfterValue": "2000000", 297 "BriefDescription": "Cycles when thread is not halted (fixed counter)" 298 }, 299 { 300 "EventCode": "0x3C", 301 "Counter": "0,1,2,3", 302 "UMask": "0x0", 303 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 304 "SampleAfterValue": "2000000", 305 "BriefDescription": "Cycles when thread is not halted (programmable counter)" 306 }, 307 { 308 "EventCode": "0x3C", 309 "Invert": "1", 310 "Counter": "0,1,2,3", 311 "UMask": "0x0", 312 "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", 313 "SampleAfterValue": "2000000", 314 "BriefDescription": "Total CPU cycles", 315 "CounterMask": "2" 316 }, 317 { 318 "EventCode": "0x87", 319 "Counter": "0,1,2,3", 320 "UMask": "0xf", 321 "EventName": "ILD_STALL.ANY", 322 "SampleAfterValue": "2000000", 323 "BriefDescription": "Any Instruction Length Decoder stall cycles" 324 }, 325 { 326 "EventCode": "0x87", 327 "Counter": "0,1,2,3", 328 "UMask": "0x4", 329 "EventName": "ILD_STALL.IQ_FULL", 330 "SampleAfterValue": "2000000", 331 "BriefDescription": "Instruction Queue full stall cycles" 332 }, 333 { 334 "EventCode": "0x87", 335 "Counter": "0,1,2,3", 336 "UMask": "0x1", 337 "EventName": "ILD_STALL.LCP", 338 "SampleAfterValue": "2000000", 339 "BriefDescription": "Length Change Prefix stall cycles" 340 }, 341 { 342 "EventCode": "0x87", 343 "Counter": "0,1,2,3", 344 "UMask": "0x2", 345 "EventName": "ILD_STALL.MRU", 346 "SampleAfterValue": "2000000", 347 "BriefDescription": "Stall cycles due to BPU MRU bypass" 348 }, 349 { 350 "EventCode": "0x87", 351 "Counter": "0,1,2,3", 352 "UMask": "0x8", 353 "EventName": "ILD_STALL.REGEN", 354 "SampleAfterValue": "2000000", 355 "BriefDescription": "Regen stall cycles" 356 }, 357 { 358 "EventCode": "0x18", 359 "Counter": "0,1,2,3", 360 "UMask": "0x1", 361 "EventName": "INST_DECODED.DEC0", 362 "SampleAfterValue": "2000000", 363 "BriefDescription": "Instructions that must be decoded by decoder 0" 364 }, 365 { 366 "EventCode": "0x1E", 367 "Counter": "0,1,2,3", 368 "UMask": "0x1", 369 "EventName": "INST_QUEUE_WRITE_CYCLES", 370 "SampleAfterValue": "2000000", 371 "BriefDescription": "Cycles instructions are written to the instruction queue" 372 }, 373 { 374 "EventCode": "0x17", 375 "Counter": "0,1,2,3", 376 "UMask": "0x1", 377 "EventName": "INST_QUEUE_WRITES", 378 "SampleAfterValue": "2000000", 379 "BriefDescription": "Instructions written to instruction queue." 380 }, 381 { 382 "EventCode": "0x0", 383 "Counter": "Fixed counter 1", 384 "UMask": "0x0", 385 "EventName": "INST_RETIRED.ANY", 386 "SampleAfterValue": "2000000", 387 "BriefDescription": "Instructions retired (fixed counter)" 388 }, 389 { 390 "PEBS": "1", 391 "EventCode": "0xC0", 392 "Counter": "0,1,2,3", 393 "UMask": "0x1", 394 "EventName": "INST_RETIRED.ANY_P", 395 "SampleAfterValue": "2000000", 396 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" 397 }, 398 { 399 "PEBS": "1", 400 "EventCode": "0xC0", 401 "Counter": "0,1,2,3", 402 "UMask": "0x4", 403 "EventName": "INST_RETIRED.MMX", 404 "SampleAfterValue": "2000000", 405 "BriefDescription": "Retired MMX instructions (Precise Event)" 406 }, 407 { 408 "PEBS": "1", 409 "EventCode": "0xC0", 410 "Invert": "1", 411 "Counter": "0,1,2,3", 412 "UMask": "0x1", 413 "EventName": "INST_RETIRED.TOTAL_CYCLES", 414 "SampleAfterValue": "2000000", 415 "BriefDescription": "Total cycles (Precise Event)", 416 "CounterMask": "16" 417 }, 418 { 419 "PEBS": "1", 420 "EventCode": "0xC0", 421 "Counter": "0,1,2,3", 422 "UMask": "0x2", 423 "EventName": "INST_RETIRED.X87", 424 "SampleAfterValue": "2000000", 425 "BriefDescription": "Retired floating-point operations (Precise Event)" 426 }, 427 { 428 "EventCode": "0x4C", 429 "Counter": "0,1", 430 "UMask": "0x1", 431 "EventName": "LOAD_HIT_PRE", 432 "SampleAfterValue": "200000", 433 "BriefDescription": "Load operations conflicting with software prefetches" 434 }, 435 { 436 "EventCode": "0xA8", 437 "Counter": "0,1,2,3", 438 "UMask": "0x1", 439 "EventName": "LSD.ACTIVE", 440 "SampleAfterValue": "2000000", 441 "BriefDescription": "Cycles when uops were delivered by the LSD", 442 "CounterMask": "1" 443 }, 444 { 445 "EventCode": "0xA8", 446 "Invert": "1", 447 "Counter": "0,1,2,3", 448 "UMask": "0x1", 449 "EventName": "LSD.INACTIVE", 450 "SampleAfterValue": "2000000", 451 "BriefDescription": "Cycles no uops were delivered by the LSD", 452 "CounterMask": "1" 453 }, 454 { 455 "EventCode": "0x20", 456 "Counter": "0,1,2,3", 457 "UMask": "0x1", 458 "EventName": "LSD_OVERFLOW", 459 "SampleAfterValue": "2000000", 460 "BriefDescription": "Loops that can't stream from the instruction queue" 461 }, 462 { 463 "EventCode": "0xC3", 464 "Counter": "0,1,2,3", 465 "UMask": "0x1", 466 "EventName": "MACHINE_CLEARS.CYCLES", 467 "SampleAfterValue": "20000", 468 "BriefDescription": "Cycles machine clear asserted" 469 }, 470 { 471 "EventCode": "0xC3", 472 "Counter": "0,1,2,3", 473 "UMask": "0x2", 474 "EventName": "MACHINE_CLEARS.MEM_ORDER", 475 "SampleAfterValue": "20000", 476 "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" 477 }, 478 { 479 "EventCode": "0xC3", 480 "Counter": "0,1,2,3", 481 "UMask": "0x4", 482 "EventName": "MACHINE_CLEARS.SMC", 483 "SampleAfterValue": "20000", 484 "BriefDescription": "Self-Modifying Code detected" 485 }, 486 { 487 "EventCode": "0xA2", 488 "Counter": "0,1,2,3", 489 "UMask": "0x1", 490 "EventName": "RESOURCE_STALLS.ANY", 491 "SampleAfterValue": "2000000", 492 "BriefDescription": "Resource related stall cycles" 493 }, 494 { 495 "EventCode": "0xA2", 496 "Counter": "0,1,2,3", 497 "UMask": "0x20", 498 "EventName": "RESOURCE_STALLS.FPCW", 499 "SampleAfterValue": "2000000", 500 "BriefDescription": "FPU control word write stall cycles" 501 }, 502 { 503 "EventCode": "0xA2", 504 "Counter": "0,1,2,3", 505 "UMask": "0x2", 506 "EventName": "RESOURCE_STALLS.LOAD", 507 "SampleAfterValue": "2000000", 508 "BriefDescription": "Load buffer stall cycles" 509 }, 510 { 511 "EventCode": "0xA2", 512 "Counter": "0,1,2,3", 513 "UMask": "0x40", 514 "EventName": "RESOURCE_STALLS.MXCSR", 515 "SampleAfterValue": "2000000", 516 "BriefDescription": "MXCSR rename stall cycles" 517 }, 518 { 519 "EventCode": "0xA2", 520 "Counter": "0,1,2,3", 521 "UMask": "0x80", 522 "EventName": "RESOURCE_STALLS.OTHER", 523 "SampleAfterValue": "2000000", 524 "BriefDescription": "Other Resource related stall cycles" 525 }, 526 { 527 "EventCode": "0xA2", 528 "Counter": "0,1,2,3", 529 "UMask": "0x10", 530 "EventName": "RESOURCE_STALLS.ROB_FULL", 531 "SampleAfterValue": "2000000", 532 "BriefDescription": "ROB full stall cycles" 533 }, 534 { 535 "EventCode": "0xA2", 536 "Counter": "0,1,2,3", 537 "UMask": "0x4", 538 "EventName": "RESOURCE_STALLS.RS_FULL", 539 "SampleAfterValue": "2000000", 540 "BriefDescription": "Reservation Station full stall cycles" 541 }, 542 { 543 "EventCode": "0xA2", 544 "Counter": "0,1,2,3", 545 "UMask": "0x8", 546 "EventName": "RESOURCE_STALLS.STORE", 547 "SampleAfterValue": "2000000", 548 "BriefDescription": "Store buffer stall cycles" 549 }, 550 { 551 "PEBS": "1", 552 "EventCode": "0xC7", 553 "Counter": "0,1,2,3", 554 "UMask": "0x4", 555 "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", 556 "SampleAfterValue": "200000", 557 "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" 558 }, 559 { 560 "PEBS": "1", 561 "EventCode": "0xC7", 562 "Counter": "0,1,2,3", 563 "UMask": "0x1", 564 "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", 565 "SampleAfterValue": "200000", 566 "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" 567 }, 568 { 569 "PEBS": "1", 570 "EventCode": "0xC7", 571 "Counter": "0,1,2,3", 572 "UMask": "0x8", 573 "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", 574 "SampleAfterValue": "200000", 575 "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" 576 }, 577 { 578 "PEBS": "1", 579 "EventCode": "0xC7", 580 "Counter": "0,1,2,3", 581 "UMask": "0x2", 582 "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", 583 "SampleAfterValue": "200000", 584 "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" 585 }, 586 { 587 "PEBS": "1", 588 "EventCode": "0xC7", 589 "Counter": "0,1,2,3", 590 "UMask": "0x10", 591 "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", 592 "SampleAfterValue": "200000", 593 "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" 594 }, 595 { 596 "EventCode": "0x3C", 597 "Counter": "0,1,2,3", 598 "UMask": "0x0", 599 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 600 "SampleAfterValue": "2000000", 601 "BriefDescription": "Cycles thread is active" 602 }, 603 { 604 "EventCode": "0xDB", 605 "Counter": "0,1,2,3", 606 "UMask": "0x1", 607 "EventName": "UOP_UNFUSION", 608 "SampleAfterValue": "2000000", 609 "BriefDescription": "Uop unfusions due to FP exceptions" 610 }, 611 { 612 "EventCode": "0xD1", 613 "Counter": "0,1,2,3", 614 "UMask": "0x4", 615 "EventName": "UOPS_DECODED.ESP_FOLDING", 616 "SampleAfterValue": "2000000", 617 "BriefDescription": "Stack pointer instructions decoded" 618 }, 619 { 620 "EventCode": "0xD1", 621 "Counter": "0,1,2,3", 622 "UMask": "0x8", 623 "EventName": "UOPS_DECODED.ESP_SYNC", 624 "SampleAfterValue": "2000000", 625 "BriefDescription": "Stack pointer sync operations" 626 }, 627 { 628 "EventCode": "0xD1", 629 "Counter": "0,1,2,3", 630 "UMask": "0x2", 631 "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", 632 "SampleAfterValue": "2000000", 633 "BriefDescription": "Uops decoded by Microcode Sequencer", 634 "CounterMask": "1" 635 }, 636 { 637 "EventCode": "0xD1", 638 "Invert": "1", 639 "Counter": "0,1,2,3", 640 "UMask": "0x1", 641 "EventName": "UOPS_DECODED.STALL_CYCLES", 642 "SampleAfterValue": "2000000", 643 "BriefDescription": "Cycles no Uops are decoded", 644 "CounterMask": "1" 645 }, 646 { 647 "EventCode": "0xB1", 648 "Counter": "0,1,2,3", 649 "UMask": "0x3f", 650 "AnyThread": "1", 651 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", 652 "SampleAfterValue": "2000000", 653 "BriefDescription": "Cycles Uops executed on any port (core count)", 654 "CounterMask": "1" 655 }, 656 { 657 "EventCode": "0xB1", 658 "Counter": "0,1,2,3", 659 "UMask": "0x1f", 660 "AnyThread": "1", 661 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", 662 "SampleAfterValue": "2000000", 663 "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", 664 "CounterMask": "1" 665 }, 666 { 667 "EventCode": "0xB1", 668 "Invert": "1", 669 "Counter": "0,1,2,3", 670 "UMask": "0x3f", 671 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", 672 "SampleAfterValue": "2000000", 673 "BriefDescription": "Uops executed on any port (core count)", 674 "CounterMask": "1", 675 "EdgeDetect": "1" 676 }, 677 { 678 "EventCode": "0xB1", 679 "Invert": "1", 680 "Counter": "0,1,2,3", 681 "UMask": "0x1f", 682 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", 683 "SampleAfterValue": "2000000", 684 "BriefDescription": "Uops executed on ports 0-4 (core count)", 685 "CounterMask": "1", 686 "EdgeDetect": "1" 687 }, 688 { 689 "EventCode": "0xB1", 690 "Invert": "1", 691 "Counter": "0,1,2,3", 692 "UMask": "0x3f", 693 "AnyThread": "1", 694 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", 695 "SampleAfterValue": "2000000", 696 "BriefDescription": "Cycles no Uops issued on any port (core count)", 697 "CounterMask": "1" 698 }, 699 { 700 "EventCode": "0xB1", 701 "Invert": "1", 702 "Counter": "0,1,2,3", 703 "UMask": "0x1f", 704 "AnyThread": "1", 705 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", 706 "SampleAfterValue": "2000000", 707 "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", 708 "CounterMask": "1" 709 }, 710 { 711 "EventCode": "0xB1", 712 "Counter": "0,1,2,3", 713 "UMask": "0x1", 714 "EventName": "UOPS_EXECUTED.PORT0", 715 "SampleAfterValue": "2000000", 716 "BriefDescription": "Uops executed on port 0" 717 }, 718 { 719 "EventCode": "0xB1", 720 "Counter": "0,1,2,3", 721 "UMask": "0x40", 722 "EventName": "UOPS_EXECUTED.PORT015", 723 "SampleAfterValue": "2000000", 724 "BriefDescription": "Uops issued on ports 0, 1 or 5" 725 }, 726 { 727 "EventCode": "0xB1", 728 "Invert": "1", 729 "Counter": "0,1,2,3", 730 "UMask": "0x40", 731 "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", 732 "SampleAfterValue": "2000000", 733 "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", 734 "CounterMask": "1" 735 }, 736 { 737 "EventCode": "0xB1", 738 "Counter": "0,1,2,3", 739 "UMask": "0x2", 740 "EventName": "UOPS_EXECUTED.PORT1", 741 "SampleAfterValue": "2000000", 742 "BriefDescription": "Uops executed on port 1" 743 }, 744 { 745 "EventCode": "0xB1", 746 "Counter": "0,1,2,3", 747 "UMask": "0x4", 748 "AnyThread": "1", 749 "EventName": "UOPS_EXECUTED.PORT2_CORE", 750 "SampleAfterValue": "2000000", 751 "BriefDescription": "Uops executed on port 2 (core count)" 752 }, 753 { 754 "EventCode": "0xB1", 755 "Counter": "0,1,2,3", 756 "UMask": "0x80", 757 "AnyThread": "1", 758 "EventName": "UOPS_EXECUTED.PORT234_CORE", 759 "SampleAfterValue": "2000000", 760 "BriefDescription": "Uops issued on ports 2, 3 or 4" 761 }, 762 { 763 "EventCode": "0xB1", 764 "Counter": "0,1,2,3", 765 "UMask": "0x8", 766 "AnyThread": "1", 767 "EventName": "UOPS_EXECUTED.PORT3_CORE", 768 "SampleAfterValue": "2000000", 769 "BriefDescription": "Uops executed on port 3 (core count)" 770 }, 771 { 772 "EventCode": "0xB1", 773 "Counter": "0,1,2,3", 774 "UMask": "0x10", 775 "AnyThread": "1", 776 "EventName": "UOPS_EXECUTED.PORT4_CORE", 777 "SampleAfterValue": "2000000", 778 "BriefDescription": "Uops executed on port 4 (core count)" 779 }, 780 { 781 "EventCode": "0xB1", 782 "Counter": "0,1,2,3", 783 "UMask": "0x20", 784 "EventName": "UOPS_EXECUTED.PORT5", 785 "SampleAfterValue": "2000000", 786 "BriefDescription": "Uops executed on port 5" 787 }, 788 { 789 "EventCode": "0xE", 790 "Counter": "0,1,2,3", 791 "UMask": "0x1", 792 "EventName": "UOPS_ISSUED.ANY", 793 "SampleAfterValue": "2000000", 794 "BriefDescription": "Uops issued" 795 }, 796 { 797 "EventCode": "0xE", 798 "Invert": "1", 799 "Counter": "0,1,2,3", 800 "UMask": "0x1", 801 "AnyThread": "1", 802 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", 803 "SampleAfterValue": "2000000", 804 "BriefDescription": "Cycles no Uops were issued on any thread", 805 "CounterMask": "1" 806 }, 807 { 808 "EventCode": "0xE", 809 "Counter": "0,1,2,3", 810 "UMask": "0x1", 811 "AnyThread": "1", 812 "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", 813 "SampleAfterValue": "2000000", 814 "BriefDescription": "Cycles Uops were issued on either thread", 815 "CounterMask": "1" 816 }, 817 { 818 "EventCode": "0xE", 819 "Counter": "0,1,2,3", 820 "UMask": "0x2", 821 "EventName": "UOPS_ISSUED.FUSED", 822 "SampleAfterValue": "2000000", 823 "BriefDescription": "Fused Uops issued" 824 }, 825 { 826 "EventCode": "0xE", 827 "Invert": "1", 828 "Counter": "0,1,2,3", 829 "UMask": "0x1", 830 "EventName": "UOPS_ISSUED.STALL_CYCLES", 831 "SampleAfterValue": "2000000", 832 "BriefDescription": "Cycles no Uops were issued", 833 "CounterMask": "1" 834 }, 835 { 836 "PEBS": "1", 837 "EventCode": "0xC2", 838 "Counter": "0,1,2,3", 839 "UMask": "0x1", 840 "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", 841 "SampleAfterValue": "2000000", 842 "BriefDescription": "Cycles Uops are being retired", 843 "CounterMask": "1" 844 }, 845 { 846 "PEBS": "1", 847 "EventCode": "0xC2", 848 "Counter": "0,1,2,3", 849 "UMask": "0x1", 850 "EventName": "UOPS_RETIRED.ANY", 851 "SampleAfterValue": "2000000", 852 "BriefDescription": "Uops retired (Precise Event)" 853 }, 854 { 855 "PEBS": "1", 856 "EventCode": "0xC2", 857 "Counter": "0,1,2,3", 858 "UMask": "0x4", 859 "EventName": "UOPS_RETIRED.MACRO_FUSED", 860 "SampleAfterValue": "2000000", 861 "BriefDescription": "Macro-fused Uops retired (Precise Event)" 862 }, 863 { 864 "PEBS": "1", 865 "EventCode": "0xC2", 866 "Counter": "0,1,2,3", 867 "UMask": "0x2", 868 "EventName": "UOPS_RETIRED.RETIRE_SLOTS", 869 "SampleAfterValue": "2000000", 870 "BriefDescription": "Retirement slots used (Precise Event)" 871 }, 872 { 873 "PEBS": "1", 874 "EventCode": "0xC2", 875 "Invert": "1", 876 "Counter": "0,1,2,3", 877 "UMask": "0x1", 878 "EventName": "UOPS_RETIRED.STALL_CYCLES", 879 "SampleAfterValue": "2000000", 880 "BriefDescription": "Cycles Uops are not retiring (Precise Event)", 881 "CounterMask": "1" 882 }, 883 { 884 "PEBS": "1", 885 "EventCode": "0xC2", 886 "Invert": "1", 887 "Counter": "0,1,2,3", 888 "UMask": "0x1", 889 "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 890 "SampleAfterValue": "2000000", 891 "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", 892 "CounterMask": "16" 893 }, 894 { 895 "PEBS": "2", 896 "EventCode": "0xC0", 897 "Invert": "1", 898 "Counter": "0,1,2,3", 899 "UMask": "0x1", 900 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", 901 "SampleAfterValue": "2000000", 902 "BriefDescription": "Total cycles (Precise Event)", 903 "CounterMask": "16" 904 } 905]