xref: /freebsd/lib/libpmc/pmu-events/arch/x86/westmereex/pipeline.json (revision 5956d97f4b3204318ceb6aa9c77bd0bc6ea87a41) 
1[
2    {
3        "BriefDescription": "Cycles the divider is busy",
4        "Counter": "0,1,2,3",
5        "EventCode": "0x14",
6        "EventName": "ARITH.CYCLES_DIV_BUSY",
7        "SampleAfterValue": "2000000",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Divide Operations executed",
12        "Counter": "0,1,2,3",
13        "CounterMask": "1",
14        "EdgeDetect": "1",
15        "EventCode": "0x14",
16        "EventName": "ARITH.DIV",
17        "Invert": "1",
18        "SampleAfterValue": "2000000",
19        "UMask": "0x1"
20    },
21    {
22        "BriefDescription": "Multiply operations executed",
23        "Counter": "0,1,2,3",
24        "EventCode": "0x14",
25        "EventName": "ARITH.MUL",
26        "SampleAfterValue": "2000000",
27        "UMask": "0x2"
28    },
29    {
30        "BriefDescription": "BACLEAR asserted with bad target address",
31        "Counter": "0,1,2,3",
32        "EventCode": "0xE6",
33        "EventName": "BACLEAR.BAD_TARGET",
34        "SampleAfterValue": "2000000",
35        "UMask": "0x2"
36    },
37    {
38        "BriefDescription": "BACLEAR asserted, regardless of cause",
39        "Counter": "0,1,2,3",
40        "EventCode": "0xE6",
41        "EventName": "BACLEAR.CLEAR",
42        "SampleAfterValue": "2000000",
43        "UMask": "0x1"
44    },
45    {
46        "BriefDescription": "Instruction queue forced BACLEAR",
47        "Counter": "0,1,2,3",
48        "EventCode": "0xA7",
49        "EventName": "BACLEAR_FORCE_IQ",
50        "SampleAfterValue": "2000000",
51        "UMask": "0x1"
52    },
53    {
54        "BriefDescription": "Early Branch Prediciton Unit clears",
55        "Counter": "0,1,2,3",
56        "EventCode": "0xE8",
57        "EventName": "BPU_CLEARS.EARLY",
58        "SampleAfterValue": "2000000",
59        "UMask": "0x1"
60    },
61    {
62        "BriefDescription": "Late Branch Prediction Unit clears",
63        "Counter": "0,1,2,3",
64        "EventCode": "0xE8",
65        "EventName": "BPU_CLEARS.LATE",
66        "SampleAfterValue": "2000000",
67        "UMask": "0x2"
68    },
69    {
70        "BriefDescription": "Branch prediction unit missed call or return",
71        "Counter": "0,1,2,3",
72        "EventCode": "0xE5",
73        "EventName": "BPU_MISSED_CALL_RET",
74        "SampleAfterValue": "2000000",
75        "UMask": "0x1"
76    },
77    {
78        "BriefDescription": "Branch instructions decoded",
79        "Counter": "0,1,2,3",
80        "EventCode": "0xE0",
81        "EventName": "BR_INST_DECODED",
82        "SampleAfterValue": "2000000",
83        "UMask": "0x1"
84    },
85    {
86        "BriefDescription": "Branch instructions executed",
87        "Counter": "0,1,2,3",
88        "EventCode": "0x88",
89        "EventName": "BR_INST_EXEC.ANY",
90        "SampleAfterValue": "200000",
91        "UMask": "0x7f"
92    },
93    {
94        "BriefDescription": "Conditional branch instructions executed",
95        "Counter": "0,1,2,3",
96        "EventCode": "0x88",
97        "EventName": "BR_INST_EXEC.COND",
98        "SampleAfterValue": "200000",
99        "UMask": "0x1"
100    },
101    {
102        "BriefDescription": "Unconditional branches executed",
103        "Counter": "0,1,2,3",
104        "EventCode": "0x88",
105        "EventName": "BR_INST_EXEC.DIRECT",
106        "SampleAfterValue": "200000",
107        "UMask": "0x2"
108    },
109    {
110        "BriefDescription": "Unconditional call branches executed",
111        "Counter": "0,1,2,3",
112        "EventCode": "0x88",
113        "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
114        "SampleAfterValue": "20000",
115        "UMask": "0x10"
116    },
117    {
118        "BriefDescription": "Indirect call branches executed",
119        "Counter": "0,1,2,3",
120        "EventCode": "0x88",
121        "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
122        "SampleAfterValue": "20000",
123        "UMask": "0x20"
124    },
125    {
126        "BriefDescription": "Indirect non call branches executed",
127        "Counter": "0,1,2,3",
128        "EventCode": "0x88",
129        "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
130        "SampleAfterValue": "20000",
131        "UMask": "0x4"
132    },
133    {
134        "BriefDescription": "Call branches executed",
135        "Counter": "0,1,2,3",
136        "EventCode": "0x88",
137        "EventName": "BR_INST_EXEC.NEAR_CALLS",
138        "SampleAfterValue": "20000",
139        "UMask": "0x30"
140    },
141    {
142        "BriefDescription": "All non call branches executed",
143        "Counter": "0,1,2,3",
144        "EventCode": "0x88",
145        "EventName": "BR_INST_EXEC.NON_CALLS",
146        "SampleAfterValue": "200000",
147        "UMask": "0x7"
148    },
149    {
150        "BriefDescription": "Indirect return branches executed",
151        "Counter": "0,1,2,3",
152        "EventCode": "0x88",
153        "EventName": "BR_INST_EXEC.RETURN_NEAR",
154        "SampleAfterValue": "20000",
155        "UMask": "0x8"
156    },
157    {
158        "BriefDescription": "Taken branches executed",
159        "Counter": "0,1,2,3",
160        "EventCode": "0x88",
161        "EventName": "BR_INST_EXEC.TAKEN",
162        "SampleAfterValue": "200000",
163        "UMask": "0x40"
164    },
165    {
166        "BriefDescription": "Retired branch instructions (Precise Event)",
167        "Counter": "0,1,2,3",
168        "EventCode": "0xC4",
169        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
170        "PEBS": "1",
171        "SampleAfterValue": "200000",
172        "UMask": "0x4"
173    },
174    {
175        "BriefDescription": "Retired conditional branch instructions (Precise Event)",
176        "Counter": "0,1,2,3",
177        "EventCode": "0xC4",
178        "EventName": "BR_INST_RETIRED.CONDITIONAL",
179        "PEBS": "1",
180        "SampleAfterValue": "200000",
181        "UMask": "0x1"
182    },
183    {
184        "BriefDescription": "Retired near call instructions (Precise Event)",
185        "Counter": "0,1,2,3",
186        "EventCode": "0xC4",
187        "EventName": "BR_INST_RETIRED.NEAR_CALL",
188        "PEBS": "1",
189        "SampleAfterValue": "20000",
190        "UMask": "0x2"
191    },
192    {
193        "BriefDescription": "Mispredicted branches executed",
194        "Counter": "0,1,2,3",
195        "EventCode": "0x89",
196        "EventName": "BR_MISP_EXEC.ANY",
197        "SampleAfterValue": "20000",
198        "UMask": "0x7f"
199    },
200    {
201        "BriefDescription": "Mispredicted conditional branches executed",
202        "Counter": "0,1,2,3",
203        "EventCode": "0x89",
204        "EventName": "BR_MISP_EXEC.COND",
205        "SampleAfterValue": "20000",
206        "UMask": "0x1"
207    },
208    {
209        "BriefDescription": "Mispredicted unconditional branches executed",
210        "Counter": "0,1,2,3",
211        "EventCode": "0x89",
212        "EventName": "BR_MISP_EXEC.DIRECT",
213        "SampleAfterValue": "20000",
214        "UMask": "0x2"
215    },
216    {
217        "BriefDescription": "Mispredicted non call branches executed",
218        "Counter": "0,1,2,3",
219        "EventCode": "0x89",
220        "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
221        "SampleAfterValue": "2000",
222        "UMask": "0x10"
223    },
224    {
225        "BriefDescription": "Mispredicted indirect call branches executed",
226        "Counter": "0,1,2,3",
227        "EventCode": "0x89",
228        "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
229        "SampleAfterValue": "2000",
230        "UMask": "0x20"
231    },
232    {
233        "BriefDescription": "Mispredicted indirect non call branches executed",
234        "Counter": "0,1,2,3",
235        "EventCode": "0x89",
236        "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
237        "SampleAfterValue": "2000",
238        "UMask": "0x4"
239    },
240    {
241        "BriefDescription": "Mispredicted call branches executed",
242        "Counter": "0,1,2,3",
243        "EventCode": "0x89",
244        "EventName": "BR_MISP_EXEC.NEAR_CALLS",
245        "SampleAfterValue": "2000",
246        "UMask": "0x30"
247    },
248    {
249        "BriefDescription": "Mispredicted non call branches executed",
250        "Counter": "0,1,2,3",
251        "EventCode": "0x89",
252        "EventName": "BR_MISP_EXEC.NON_CALLS",
253        "SampleAfterValue": "20000",
254        "UMask": "0x7"
255    },
256    {
257        "BriefDescription": "Mispredicted return branches executed",
258        "Counter": "0,1,2,3",
259        "EventCode": "0x89",
260        "EventName": "BR_MISP_EXEC.RETURN_NEAR",
261        "SampleAfterValue": "2000",
262        "UMask": "0x8"
263    },
264    {
265        "BriefDescription": "Mispredicted taken branches executed",
266        "Counter": "0,1,2,3",
267        "EventCode": "0x89",
268        "EventName": "BR_MISP_EXEC.TAKEN",
269        "SampleAfterValue": "20000",
270        "UMask": "0x40"
271    },
272    {
273        "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
274        "Counter": "0,1,2,3",
275        "EventCode": "0xC5",
276        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
277        "PEBS": "1",
278        "SampleAfterValue": "20000",
279        "UMask": "0x4"
280    },
281    {
282        "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
283        "Counter": "0,1,2,3",
284        "EventCode": "0xC5",
285        "EventName": "BR_MISP_RETIRED.CONDITIONAL",
286        "PEBS": "1",
287        "SampleAfterValue": "20000",
288        "UMask": "0x1"
289    },
290    {
291        "BriefDescription": "Mispredicted near retired calls (Precise Event)",
292        "Counter": "0,1,2,3",
293        "EventCode": "0xC5",
294        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
295        "PEBS": "1",
296        "SampleAfterValue": "2000",
297        "UMask": "0x2"
298    },
299    {
300        "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
301        "Counter": "Fixed counter 3",
302        "EventCode": "0x0",
303        "EventName": "CPU_CLK_UNHALTED.REF",
304        "SampleAfterValue": "2000000",
305        "UMask": "0x0"
306    },
307    {
308        "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
309        "Counter": "0,1,2,3",
310        "EventCode": "0x3C",
311        "EventName": "CPU_CLK_UNHALTED.REF_P",
312        "SampleAfterValue": "100000",
313        "UMask": "0x1"
314    },
315    {
316        "BriefDescription": "Cycles when thread is not halted (fixed counter)",
317        "Counter": "Fixed counter 2",
318        "EventCode": "0x0",
319        "EventName": "CPU_CLK_UNHALTED.THREAD",
320        "SampleAfterValue": "2000000",
321        "UMask": "0x0"
322    },
323    {
324        "BriefDescription": "Cycles when thread is not halted (programmable counter)",
325        "Counter": "0,1,2,3",
326        "EventCode": "0x3C",
327        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
328        "SampleAfterValue": "2000000",
329        "UMask": "0x0"
330    },
331    {
332        "BriefDescription": "Total CPU cycles",
333        "Counter": "0,1,2,3",
334        "CounterMask": "2",
335        "EventCode": "0x3C",
336        "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
337        "Invert": "1",
338        "SampleAfterValue": "2000000",
339        "UMask": "0x0"
340    },
341    {
342        "BriefDescription": "Any Instruction Length Decoder stall cycles",
343        "Counter": "0,1,2,3",
344        "EventCode": "0x87",
345        "EventName": "ILD_STALL.ANY",
346        "SampleAfterValue": "2000000",
347        "UMask": "0xf"
348    },
349    {
350        "BriefDescription": "Instruction Queue full stall cycles",
351        "Counter": "0,1,2,3",
352        "EventCode": "0x87",
353        "EventName": "ILD_STALL.IQ_FULL",
354        "SampleAfterValue": "2000000",
355        "UMask": "0x4"
356    },
357    {
358        "BriefDescription": "Length Change Prefix stall cycles",
359        "Counter": "0,1,2,3",
360        "EventCode": "0x87",
361        "EventName": "ILD_STALL.LCP",
362        "SampleAfterValue": "2000000",
363        "UMask": "0x1"
364    },
365    {
366        "BriefDescription": "Stall cycles due to BPU MRU bypass",
367        "Counter": "0,1,2,3",
368        "EventCode": "0x87",
369        "EventName": "ILD_STALL.MRU",
370        "SampleAfterValue": "2000000",
371        "UMask": "0x2"
372    },
373    {
374        "BriefDescription": "Regen stall cycles",
375        "Counter": "0,1,2,3",
376        "EventCode": "0x87",
377        "EventName": "ILD_STALL.REGEN",
378        "SampleAfterValue": "2000000",
379        "UMask": "0x8"
380    },
381    {
382        "BriefDescription": "Instructions that must be decoded by decoder 0",
383        "Counter": "0,1,2,3",
384        "EventCode": "0x18",
385        "EventName": "INST_DECODED.DEC0",
386        "SampleAfterValue": "2000000",
387        "UMask": "0x1"
388    },
389    {
390        "BriefDescription": "Instructions written to instruction queue.",
391        "Counter": "0,1,2,3",
392        "EventCode": "0x17",
393        "EventName": "INST_QUEUE_WRITES",
394        "SampleAfterValue": "2000000",
395        "UMask": "0x1"
396    },
397    {
398        "BriefDescription": "Cycles instructions are written to the instruction queue",
399        "Counter": "0,1,2,3",
400        "EventCode": "0x1E",
401        "EventName": "INST_QUEUE_WRITE_CYCLES",
402        "SampleAfterValue": "2000000",
403        "UMask": "0x1"
404    },
405    {
406        "BriefDescription": "Instructions retired (fixed counter)",
407        "Counter": "Fixed counter 1",
408        "EventCode": "0x0",
409        "EventName": "INST_RETIRED.ANY",
410        "SampleAfterValue": "2000000",
411        "UMask": "0x0"
412    },
413    {
414        "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
415        "Counter": "0,1,2,3",
416        "EventCode": "0xC0",
417        "EventName": "INST_RETIRED.ANY_P",
418        "PEBS": "1",
419        "SampleAfterValue": "2000000",
420        "UMask": "0x1"
421    },
422    {
423        "BriefDescription": "Retired MMX instructions (Precise Event)",
424        "Counter": "0,1,2,3",
425        "EventCode": "0xC0",
426        "EventName": "INST_RETIRED.MMX",
427        "PEBS": "1",
428        "SampleAfterValue": "2000000",
429        "UMask": "0x4"
430    },
431    {
432        "BriefDescription": "Total cycles (Precise Event)",
433        "Counter": "0,1,2,3",
434        "CounterMask": "16",
435        "EventCode": "0xC0",
436        "EventName": "INST_RETIRED.TOTAL_CYCLES",
437        "Invert": "1",
438        "PEBS": "1",
439        "SampleAfterValue": "2000000",
440        "UMask": "0x1"
441    },
442    {
443        "BriefDescription": "Total cycles (Precise Event)",
444        "Counter": "0,1,2,3",
445        "CounterMask": "16",
446        "EventCode": "0xC0",
447        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
448        "Invert": "1",
449        "PEBS": "2",
450        "SampleAfterValue": "2000000",
451        "UMask": "0x1"
452    },
453    {
454        "BriefDescription": "Retired floating-point operations (Precise Event)",
455        "Counter": "0,1,2,3",
456        "EventCode": "0xC0",
457        "EventName": "INST_RETIRED.X87",
458        "PEBS": "1",
459        "SampleAfterValue": "2000000",
460        "UMask": "0x2"
461    },
462    {
463        "BriefDescription": "Load operations conflicting with software prefetches",
464        "Counter": "0,1",
465        "EventCode": "0x4C",
466        "EventName": "LOAD_HIT_PRE",
467        "SampleAfterValue": "200000",
468        "UMask": "0x1"
469    },
470    {
471        "BriefDescription": "Cycles when uops were delivered by the LSD",
472        "Counter": "0,1,2,3",
473        "CounterMask": "1",
474        "EventCode": "0xA8",
475        "EventName": "LSD.ACTIVE",
476        "SampleAfterValue": "2000000",
477        "UMask": "0x1"
478    },
479    {
480        "BriefDescription": "Cycles no uops were delivered by the LSD",
481        "Counter": "0,1,2,3",
482        "CounterMask": "1",
483        "EventCode": "0xA8",
484        "EventName": "LSD.INACTIVE",
485        "Invert": "1",
486        "SampleAfterValue": "2000000",
487        "UMask": "0x1"
488    },
489    {
490        "BriefDescription": "Loops that can't stream from the instruction queue",
491        "Counter": "0,1,2,3",
492        "EventCode": "0x20",
493        "EventName": "LSD_OVERFLOW",
494        "SampleAfterValue": "2000000",
495        "UMask": "0x1"
496    },
497    {
498        "BriefDescription": "Cycles machine clear asserted",
499        "Counter": "0,1,2,3",
500        "EventCode": "0xC3",
501        "EventName": "MACHINE_CLEARS.CYCLES",
502        "SampleAfterValue": "20000",
503        "UMask": "0x1"
504    },
505    {
506        "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
507        "Counter": "0,1,2,3",
508        "EventCode": "0xC3",
509        "EventName": "MACHINE_CLEARS.MEM_ORDER",
510        "SampleAfterValue": "20000",
511        "UMask": "0x2"
512    },
513    {
514        "BriefDescription": "Self-Modifying Code detected",
515        "Counter": "0,1,2,3",
516        "EventCode": "0xC3",
517        "EventName": "MACHINE_CLEARS.SMC",
518        "SampleAfterValue": "20000",
519        "UMask": "0x4"
520    },
521    {
522        "BriefDescription": "All RAT stall cycles",
523        "Counter": "0,1,2,3",
524        "EventCode": "0xD2",
525        "EventName": "RAT_STALLS.ANY",
526        "SampleAfterValue": "2000000",
527        "UMask": "0xf"
528    },
529    {
530        "BriefDescription": "Flag stall cycles",
531        "Counter": "0,1,2,3",
532        "EventCode": "0xD2",
533        "EventName": "RAT_STALLS.FLAGS",
534        "SampleAfterValue": "2000000",
535        "UMask": "0x1"
536    },
537    {
538        "BriefDescription": "Partial register stall cycles",
539        "Counter": "0,1,2,3",
540        "EventCode": "0xD2",
541        "EventName": "RAT_STALLS.REGISTERS",
542        "SampleAfterValue": "2000000",
543        "UMask": "0x2"
544    },
545    {
546        "BriefDescription": "ROB read port stalls cycles",
547        "Counter": "0,1,2,3",
548        "EventCode": "0xD2",
549        "EventName": "RAT_STALLS.ROB_READ_PORT",
550        "SampleAfterValue": "2000000",
551        "UMask": "0x4"
552    },
553    {
554        "BriefDescription": "Scoreboard stall cycles",
555        "Counter": "0,1,2,3",
556        "EventCode": "0xD2",
557        "EventName": "RAT_STALLS.SCOREBOARD",
558        "SampleAfterValue": "2000000",
559        "UMask": "0x8"
560    },
561    {
562        "BriefDescription": "Resource related stall cycles",
563        "Counter": "0,1,2,3",
564        "EventCode": "0xA2",
565        "EventName": "RESOURCE_STALLS.ANY",
566        "SampleAfterValue": "2000000",
567        "UMask": "0x1"
568    },
569    {
570        "BriefDescription": "FPU control word write stall cycles",
571        "Counter": "0,1,2,3",
572        "EventCode": "0xA2",
573        "EventName": "RESOURCE_STALLS.FPCW",
574        "SampleAfterValue": "2000000",
575        "UMask": "0x20"
576    },
577    {
578        "BriefDescription": "Load buffer stall cycles",
579        "Counter": "0,1,2,3",
580        "EventCode": "0xA2",
581        "EventName": "RESOURCE_STALLS.LOAD",
582        "SampleAfterValue": "2000000",
583        "UMask": "0x2"
584    },
585    {
586        "BriefDescription": "MXCSR rename stall cycles",
587        "Counter": "0,1,2,3",
588        "EventCode": "0xA2",
589        "EventName": "RESOURCE_STALLS.MXCSR",
590        "SampleAfterValue": "2000000",
591        "UMask": "0x40"
592    },
593    {
594        "BriefDescription": "Other Resource related stall cycles",
595        "Counter": "0,1,2,3",
596        "EventCode": "0xA2",
597        "EventName": "RESOURCE_STALLS.OTHER",
598        "SampleAfterValue": "2000000",
599        "UMask": "0x80"
600    },
601    {
602        "BriefDescription": "ROB full stall cycles",
603        "Counter": "0,1,2,3",
604        "EventCode": "0xA2",
605        "EventName": "RESOURCE_STALLS.ROB_FULL",
606        "SampleAfterValue": "2000000",
607        "UMask": "0x10"
608    },
609    {
610        "BriefDescription": "Reservation Station full stall cycles",
611        "Counter": "0,1,2,3",
612        "EventCode": "0xA2",
613        "EventName": "RESOURCE_STALLS.RS_FULL",
614        "SampleAfterValue": "2000000",
615        "UMask": "0x4"
616    },
617    {
618        "BriefDescription": "Store buffer stall cycles",
619        "Counter": "0,1,2,3",
620        "EventCode": "0xA2",
621        "EventName": "RESOURCE_STALLS.STORE",
622        "SampleAfterValue": "2000000",
623        "UMask": "0x8"
624    },
625    {
626        "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
627        "Counter": "0,1,2,3",
628        "EventCode": "0xC7",
629        "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
630        "PEBS": "1",
631        "SampleAfterValue": "200000",
632        "UMask": "0x4"
633    },
634    {
635        "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
636        "Counter": "0,1,2,3",
637        "EventCode": "0xC7",
638        "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
639        "PEBS": "1",
640        "SampleAfterValue": "200000",
641        "UMask": "0x1"
642    },
643    {
644        "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
645        "Counter": "0,1,2,3",
646        "EventCode": "0xC7",
647        "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
648        "PEBS": "1",
649        "SampleAfterValue": "200000",
650        "UMask": "0x8"
651    },
652    {
653        "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
654        "Counter": "0,1,2,3",
655        "EventCode": "0xC7",
656        "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
657        "PEBS": "1",
658        "SampleAfterValue": "200000",
659        "UMask": "0x2"
660    },
661    {
662        "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
663        "Counter": "0,1,2,3",
664        "EventCode": "0xC7",
665        "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
666        "PEBS": "1",
667        "SampleAfterValue": "200000",
668        "UMask": "0x10"
669    },
670    {
671        "BriefDescription": "Stack pointer instructions decoded",
672        "Counter": "0,1,2,3",
673        "EventCode": "0xD1",
674        "EventName": "UOPS_DECODED.ESP_FOLDING",
675        "SampleAfterValue": "2000000",
676        "UMask": "0x4"
677    },
678    {
679        "BriefDescription": "Stack pointer sync operations",
680        "Counter": "0,1,2,3",
681        "EventCode": "0xD1",
682        "EventName": "UOPS_DECODED.ESP_SYNC",
683        "SampleAfterValue": "2000000",
684        "UMask": "0x8"
685    },
686    {
687        "BriefDescription": "Uops decoded by Microcode Sequencer",
688        "Counter": "0,1,2,3",
689        "CounterMask": "1",
690        "EventCode": "0xD1",
691        "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
692        "SampleAfterValue": "2000000",
693        "UMask": "0x2"
694    },
695    {
696        "BriefDescription": "Cycles no Uops are decoded",
697        "Counter": "0,1,2,3",
698        "CounterMask": "1",
699        "EventCode": "0xD1",
700        "EventName": "UOPS_DECODED.STALL_CYCLES",
701        "Invert": "1",
702        "SampleAfterValue": "2000000",
703        "UMask": "0x1"
704    },
705    {
706        "AnyThread": "1",
707        "BriefDescription": "Cycles Uops executed on any port (core count)",
708        "Counter": "0,1,2,3",
709        "CounterMask": "1",
710        "EventCode": "0xB1",
711        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
712        "SampleAfterValue": "2000000",
713        "UMask": "0x3f"
714    },
715    {
716        "AnyThread": "1",
717        "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
718        "Counter": "0,1,2,3",
719        "CounterMask": "1",
720        "EventCode": "0xB1",
721        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
722        "SampleAfterValue": "2000000",
723        "UMask": "0x1f"
724    },
725    {
726        "BriefDescription": "Uops executed on any port (core count)",
727        "Counter": "0,1,2,3",
728        "CounterMask": "1",
729        "EdgeDetect": "1",
730        "EventCode": "0xB1",
731        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
732        "Invert": "1",
733        "SampleAfterValue": "2000000",
734        "UMask": "0x3f"
735    },
736    {
737        "BriefDescription": "Uops executed on ports 0-4 (core count)",
738        "Counter": "0,1,2,3",
739        "CounterMask": "1",
740        "EdgeDetect": "1",
741        "EventCode": "0xB1",
742        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
743        "Invert": "1",
744        "SampleAfterValue": "2000000",
745        "UMask": "0x1f"
746    },
747    {
748        "AnyThread": "1",
749        "BriefDescription": "Cycles no Uops issued on any port (core count)",
750        "Counter": "0,1,2,3",
751        "CounterMask": "1",
752        "EventCode": "0xB1",
753        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
754        "Invert": "1",
755        "SampleAfterValue": "2000000",
756        "UMask": "0x3f"
757    },
758    {
759        "AnyThread": "1",
760        "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
761        "Counter": "0,1,2,3",
762        "CounterMask": "1",
763        "EventCode": "0xB1",
764        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
765        "Invert": "1",
766        "SampleAfterValue": "2000000",
767        "UMask": "0x1f"
768    },
769    {
770        "BriefDescription": "Uops executed on port 0",
771        "Counter": "0,1,2,3",
772        "EventCode": "0xB1",
773        "EventName": "UOPS_EXECUTED.PORT0",
774        "SampleAfterValue": "2000000",
775        "UMask": "0x1"
776    },
777    {
778        "BriefDescription": "Uops issued on ports 0, 1 or 5",
779        "Counter": "0,1,2,3",
780        "EventCode": "0xB1",
781        "EventName": "UOPS_EXECUTED.PORT015",
782        "SampleAfterValue": "2000000",
783        "UMask": "0x40"
784    },
785    {
786        "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
787        "Counter": "0,1,2,3",
788        "CounterMask": "1",
789        "EventCode": "0xB1",
790        "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
791        "Invert": "1",
792        "SampleAfterValue": "2000000",
793        "UMask": "0x40"
794    },
795    {
796        "BriefDescription": "Uops executed on port 1",
797        "Counter": "0,1,2,3",
798        "EventCode": "0xB1",
799        "EventName": "UOPS_EXECUTED.PORT1",
800        "SampleAfterValue": "2000000",
801        "UMask": "0x2"
802    },
803    {
804        "AnyThread": "1",
805        "BriefDescription": "Uops issued on ports 2, 3 or 4",
806        "Counter": "0,1,2,3",
807        "EventCode": "0xB1",
808        "EventName": "UOPS_EXECUTED.PORT234_CORE",
809        "SampleAfterValue": "2000000",
810        "UMask": "0x80"
811    },
812    {
813        "AnyThread": "1",
814        "BriefDescription": "Uops executed on port 2 (core count)",
815        "Counter": "0,1,2,3",
816        "EventCode": "0xB1",
817        "EventName": "UOPS_EXECUTED.PORT2_CORE",
818        "SampleAfterValue": "2000000",
819        "UMask": "0x4"
820    },
821    {
822        "AnyThread": "1",
823        "BriefDescription": "Uops executed on port 3 (core count)",
824        "Counter": "0,1,2,3",
825        "EventCode": "0xB1",
826        "EventName": "UOPS_EXECUTED.PORT3_CORE",
827        "SampleAfterValue": "2000000",
828        "UMask": "0x8"
829    },
830    {
831        "AnyThread": "1",
832        "BriefDescription": "Uops executed on port 4 (core count)",
833        "Counter": "0,1,2,3",
834        "EventCode": "0xB1",
835        "EventName": "UOPS_EXECUTED.PORT4_CORE",
836        "SampleAfterValue": "2000000",
837        "UMask": "0x10"
838    },
839    {
840        "BriefDescription": "Uops executed on port 5",
841        "Counter": "0,1,2,3",
842        "EventCode": "0xB1",
843        "EventName": "UOPS_EXECUTED.PORT5",
844        "SampleAfterValue": "2000000",
845        "UMask": "0x20"
846    },
847    {
848        "BriefDescription": "Uops issued",
849        "Counter": "0,1,2,3",
850        "EventCode": "0xE",
851        "EventName": "UOPS_ISSUED.ANY",
852        "SampleAfterValue": "2000000",
853        "UMask": "0x1"
854    },
855    {
856        "AnyThread": "1",
857        "BriefDescription": "Cycles no Uops were issued on any thread",
858        "Counter": "0,1,2,3",
859        "CounterMask": "1",
860        "EventCode": "0xE",
861        "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
862        "Invert": "1",
863        "SampleAfterValue": "2000000",
864        "UMask": "0x1"
865    },
866    {
867        "AnyThread": "1",
868        "BriefDescription": "Cycles Uops were issued on either thread",
869        "Counter": "0,1,2,3",
870        "CounterMask": "1",
871        "EventCode": "0xE",
872        "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
873        "SampleAfterValue": "2000000",
874        "UMask": "0x1"
875    },
876    {
877        "BriefDescription": "Fused Uops issued",
878        "Counter": "0,1,2,3",
879        "EventCode": "0xE",
880        "EventName": "UOPS_ISSUED.FUSED",
881        "SampleAfterValue": "2000000",
882        "UMask": "0x2"
883    },
884    {
885        "BriefDescription": "Cycles no Uops were issued",
886        "Counter": "0,1,2,3",
887        "CounterMask": "1",
888        "EventCode": "0xE",
889        "EventName": "UOPS_ISSUED.STALL_CYCLES",
890        "Invert": "1",
891        "SampleAfterValue": "2000000",
892        "UMask": "0x1"
893    },
894    {
895        "BriefDescription": "Cycles Uops are being retired",
896        "Counter": "0,1,2,3",
897        "CounterMask": "1",
898        "EventCode": "0xC2",
899        "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
900        "PEBS": "1",
901        "SampleAfterValue": "2000000",
902        "UMask": "0x1"
903    },
904    {
905        "BriefDescription": "Uops retired (Precise Event)",
906        "Counter": "0,1,2,3",
907        "EventCode": "0xC2",
908        "EventName": "UOPS_RETIRED.ANY",
909        "PEBS": "1",
910        "SampleAfterValue": "2000000",
911        "UMask": "0x1"
912    },
913    {
914        "BriefDescription": "Macro-fused Uops retired (Precise Event)",
915        "Counter": "0,1,2,3",
916        "EventCode": "0xC2",
917        "EventName": "UOPS_RETIRED.MACRO_FUSED",
918        "PEBS": "1",
919        "SampleAfterValue": "2000000",
920        "UMask": "0x4"
921    },
922    {
923        "BriefDescription": "Retirement slots used (Precise Event)",
924        "Counter": "0,1,2,3",
925        "EventCode": "0xC2",
926        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
927        "PEBS": "1",
928        "SampleAfterValue": "2000000",
929        "UMask": "0x2"
930    },
931    {
932        "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
933        "Counter": "0,1,2,3",
934        "CounterMask": "1",
935        "EventCode": "0xC2",
936        "EventName": "UOPS_RETIRED.STALL_CYCLES",
937        "Invert": "1",
938        "PEBS": "1",
939        "SampleAfterValue": "2000000",
940        "UMask": "0x1"
941    },
942    {
943        "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
944        "Counter": "0,1,2,3",
945        "CounterMask": "16",
946        "EventCode": "0xC2",
947        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
948        "Invert": "1",
949        "PEBS": "1",
950        "SampleAfterValue": "2000000",
951        "UMask": "0x1"
952    },
953    {
954        "BriefDescription": "Uop unfusions due to FP exceptions",
955        "Counter": "0,1,2,3",
956        "EventCode": "0xDB",
957        "EventName": "UOP_UNFUSION",
958        "SampleAfterValue": "2000000",
959        "UMask": "0x1"
960    }
961]
962