1[ 2 { 3 "BriefDescription": "ES segment renames", 4 "Counter": "0,1,2,3", 5 "EventCode": "0xD5", 6 "EventName": "ES_REG_RENAMES", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "I/O transactions", 12 "Counter": "0,1,2,3", 13 "EventCode": "0x6C", 14 "EventName": "IO_TRANSACTIONS", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1I instruction fetch stall cycles", 20 "Counter": "0,1,2,3", 21 "EventCode": "0x80", 22 "EventName": "L1I.CYCLES_STALLED", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1I instruction fetch hits", 28 "Counter": "0,1,2,3", 29 "EventCode": "0x80", 30 "EventName": "L1I.HITS", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x1" 33 }, 34 { 35 "BriefDescription": "L1I instruction fetch misses", 36 "Counter": "0,1,2,3", 37 "EventCode": "0x80", 38 "EventName": "L1I.MISSES", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x2" 41 }, 42 { 43 "BriefDescription": "L1I Instruction fetches", 44 "Counter": "0,1,2,3", 45 "EventCode": "0x80", 46 "EventName": "L1I.READS", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x3" 49 }, 50 { 51 "BriefDescription": "Large ITLB hit", 52 "Counter": "0,1,2,3", 53 "EventCode": "0x82", 54 "EventName": "LARGE_ITLB.HIT", 55 "SampleAfterValue": "200000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "Loads that partially overlap an earlier store", 60 "Counter": "0,1,2,3", 61 "EventCode": "0x3", 62 "EventName": "LOAD_BLOCK.OVERLAP_STORE", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "All loads dispatched", 68 "Counter": "0,1,2,3", 69 "EventCode": "0x13", 70 "EventName": "LOAD_DISPATCH.ANY", 71 "SampleAfterValue": "2000000", 72 "UMask": "0x7" 73 }, 74 { 75 "BriefDescription": "Loads dispatched from the MOB", 76 "Counter": "0,1,2,3", 77 "EventCode": "0x13", 78 "EventName": "LOAD_DISPATCH.MOB", 79 "SampleAfterValue": "2000000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "Loads dispatched that bypass the MOB", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x13", 86 "EventName": "LOAD_DISPATCH.RS", 87 "SampleAfterValue": "2000000", 88 "UMask": "0x1" 89 }, 90 { 91 "BriefDescription": "Loads dispatched from stage 305", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x13", 94 "EventName": "LOAD_DISPATCH.RS_DELAYED", 95 "SampleAfterValue": "2000000", 96 "UMask": "0x2" 97 }, 98 { 99 "BriefDescription": "False dependencies due to partial address aliasing", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x7", 102 "EventName": "PARTIAL_ADDRESS_ALIAS", 103 "SampleAfterValue": "200000", 104 "UMask": "0x1" 105 }, 106 { 107 "BriefDescription": "All Store buffer stall cycles", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x4", 110 "EventName": "SB_DRAIN.ANY", 111 "SampleAfterValue": "200000", 112 "UMask": "0x7" 113 }, 114 { 115 "BriefDescription": "Segment rename stall cycles", 116 "Counter": "0,1,2,3", 117 "EventCode": "0xD4", 118 "EventName": "SEG_RENAME_STALLS", 119 "SampleAfterValue": "2000000", 120 "UMask": "0x1" 121 }, 122 { 123 "BriefDescription": "Snoop code requests", 124 "Counter": "0,1,2,3", 125 "EventCode": "0xB4", 126 "EventName": "SNOOPQ_REQUESTS.CODE", 127 "SampleAfterValue": "100000", 128 "UMask": "0x4" 129 }, 130 { 131 "BriefDescription": "Snoop data requests", 132 "Counter": "0,1,2,3", 133 "EventCode": "0xB4", 134 "EventName": "SNOOPQ_REQUESTS.DATA", 135 "SampleAfterValue": "100000", 136 "UMask": "0x1" 137 }, 138 { 139 "BriefDescription": "Snoop invalidate requests", 140 "Counter": "0,1,2,3", 141 "EventCode": "0xB4", 142 "EventName": "SNOOPQ_REQUESTS.INVALIDATE", 143 "SampleAfterValue": "100000", 144 "UMask": "0x2" 145 }, 146 { 147 "BriefDescription": "Outstanding snoop code requests", 148 "EventCode": "0xB3", 149 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", 150 "SampleAfterValue": "2000000", 151 "UMask": "0x4" 152 }, 153 { 154 "BriefDescription": "Cycles snoop code requests queued", 155 "CounterMask": "1", 156 "EventCode": "0xB3", 157 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", 158 "SampleAfterValue": "2000000", 159 "UMask": "0x4" 160 }, 161 { 162 "BriefDescription": "Outstanding snoop data requests", 163 "EventCode": "0xB3", 164 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", 165 "SampleAfterValue": "2000000", 166 "UMask": "0x1" 167 }, 168 { 169 "BriefDescription": "Cycles snoop data requests queued", 170 "CounterMask": "1", 171 "EventCode": "0xB3", 172 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", 173 "SampleAfterValue": "2000000", 174 "UMask": "0x1" 175 }, 176 { 177 "BriefDescription": "Outstanding snoop invalidate requests", 178 "EventCode": "0xB3", 179 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", 180 "SampleAfterValue": "2000000", 181 "UMask": "0x2" 182 }, 183 { 184 "BriefDescription": "Cycles snoop invalidate requests queued", 185 "CounterMask": "1", 186 "EventCode": "0xB3", 187 "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", 188 "SampleAfterValue": "2000000", 189 "UMask": "0x2" 190 }, 191 { 192 "BriefDescription": "Thread responded HIT to snoop", 193 "Counter": "0,1,2,3", 194 "EventCode": "0xB8", 195 "EventName": "SNOOP_RESPONSE.HIT", 196 "SampleAfterValue": "100000", 197 "UMask": "0x1" 198 }, 199 { 200 "BriefDescription": "Thread responded HITE to snoop", 201 "Counter": "0,1,2,3", 202 "EventCode": "0xB8", 203 "EventName": "SNOOP_RESPONSE.HITE", 204 "SampleAfterValue": "100000", 205 "UMask": "0x2" 206 }, 207 { 208 "BriefDescription": "Thread responded HITM to snoop", 209 "Counter": "0,1,2,3", 210 "EventCode": "0xB8", 211 "EventName": "SNOOP_RESPONSE.HITM", 212 "SampleAfterValue": "100000", 213 "UMask": "0x4" 214 }, 215 { 216 "BriefDescription": "Super Queue full stall cycles", 217 "Counter": "0,1,2,3", 218 "EventCode": "0xF6", 219 "EventName": "SQ_FULL_STALL_CYCLES", 220 "SampleAfterValue": "2000000", 221 "UMask": "0x1" 222 } 223] 224